Woo-Yeol Shin

A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface

With the scaling of CMOS transistors and advance in I/O circuitry, the data rate of memory interfaces has recently reached 16Gb/s per channel [1], in which a point-to-point channel is required rather than a multi-drop channel for the high data rate. While point-to-point channels are advantageous in achieving higher data rates because of the absence of undesired reflections that occur at each stub of multi-drop channels, they are not suitable for high-capacity, high-throughput memory systems such as transaction servers or cloud computing nodes due to their prohibitively large PCB routing area connecting the memory chips. FBDIMM [2] and the cascading memory architecture [3] aim to reduce the routing area by the use of daisy-chained configurations, but they suffer from increased latency problems. This is why the recent DDR2/3 memory interface still uses the multi-drop bus architecture called stub series terminated logic (SSTL), and a number of proposals have been made to mitigate the problem of stub reflections in SSTL. For instance, a decision feedback equalizer has been used [4] to cancel the inter-symbol interference (ISI) due to stub reflections; but this requires a large number of filter taps, resulting in a limited speed under 3Gb/s. Another approach to eliminate impedance discontinuity is to use a 2Z0 ohm transmission line [5], but this scheme is only applicable to 2-slot configurations.

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers

In wide fan-in dynamic multiplexers, the two phase evaluate-precharge operation leads to high switching activity at the dynamic and the output nodes introducing a significant power penalty. To address this issue, the switching-aware design techniques are being explored but these existing techniques suffer from design inflexibilities. In this paper, we propose a pulse domino switching-aware technique, called SSPD, to reduce the overall power consumption of a wide fan-in dynamic gate by having static-like switching behavior at the dynamic node, and the gate input/output terminals. A conditional pulse generator is also proposed, which enables the SSPD multiplexers to be easily adapted to a wide set of noise and delay specifications. Simulation results of 8-bit and 16-bit dynamic multiplexers designed and simulated in a 1.2-V 90-nm CMOS process show that the SSPD technique can reduce the average power by up to 21% and 36%, respectively, when compared to the conventional footless domino technique.

A fast-acquisition PLL using split half-duty sampled feedforward loop filter

We reduce the pattern jitter and acquisition time of a phase-locked loop (PLL) by adopting the split half-duty sampled feedforward loop filter. A prototype designed and fabricated in a 0.18μm standard CMOS technology has a 40% lower acquisition time than a PLL without operating in fast acquisition mode. Its peak-to-peak jitter is 26% less than that of a PLL with a conventional 2nd-order RC loop filter.

A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM to have advanced design techniques. Proposed LPDDR4 in this paper achieves over 30% improved power efficiency and over 4.3Gbps data rate with 1.1V supply voltage. These are challenging target comparing with that of LPDDR3. This works includes various techniques including multi-channel per die, various trainings, low swing interface, DQS and clock frequency dividing, internal reference voltage for data and command-address signals and so on. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

A 5-Gb/s digitally controlled 3-tap DFE receiver for serial communications

Decision feedback equalizers (DFEs) play a critical role in high-speed communications through band-limited channels. We implemented a 3-tap DFE receiver for 5-Gb/s data bandwidth. To realize a multi-tap DFE operation, a digital-control scheme is proposed that does not use analog circuits for biasing, such as DACs. In addition to the conventional loop unrolling, several techniques including combined feedback are used to reduce the latency of the feedback path. Fabricated in a 0.13-μm CMOS process, the prototype of the proposed DFE core has an area of 0.009 mm2 and consumes 8.4 mW from a 1.2-V supply, achieving a BER of less than 10−11 over a pair of 28-inch Nelco 4000–6 board traces.

A 1.74mW/GHz 0.11–2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers

A 180° phase-shift digital delay-locked loop (DLL) for LPDDR4 memory controllers is composed of a global DLL and a local DLL for each channel. The global DLL uses a time-to-digital converter to achieve fast-locking, and then shuts down to reduce power consumption. The local DLL, locking based on delay codes from the global DLL, uses a digital window phase detector (PD) and tracks the input clock phase to compensate for process, voltage, and temperature variations. Repeatedly controlled window size of the digital window PD in this local DLL reduces the high-frequency jitter compared to the DLL using bang-bang PD. Implemented in 65nm CMOS process, proposed digital DLL dissipates 1.74mW/GHz and occupies 0.074mm2. It operates over a frequency range of 0.11-2.5GHz, and locks within 6 cycles at 0.11GHz and within 17 cycles at 2.5GHz. At 2.5GHz, the integrated jitter of the DLL output clock with the digital window PD is 953fsrms and the long-term jitter of it is 2.64psrms and 20.6pspp.

Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism

We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudo-random manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.