Gi-Moon Hong

A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface

With the scaling of CMOS transistors and advance in I/O circuitry, the data rate of memory interfaces has recently reached 16Gb/s per channel [1], in which a point-to-point channel is required rather than a multi-drop channel for the high data rate. While point-to-point channels are advantageous in achieving higher data rates because of the absence of undesired reflections that occur at each stub of multi-drop channels, they are not suitable for high-capacity, high-throughput memory systems such as transaction servers or cloud computing nodes due to their prohibitively large PCB routing area connecting the memory chips. FBDIMM [2] and the cascading memory architecture [3] aim to reduce the routing area by the use of daisy-chained configurations, but they suffer from increased latency problems. This is why the recent DDR2/3 memory interface still uses the multi-drop bus architecture called stub series terminated logic (SSTL), and a number of proposals have been made to mitigate the problem of stub reflections in SSTL. For instance, a decision feedback equalizer has been used [4] to cancel the inter-symbol interference (ISI) due to stub reflections; but this requires a large number of filter taps, resulting in a limited speed under 3Gb/s. Another approach to eliminate impedance discontinuity is to use a 2Z0 ohm transmission line [5], but this scheme is only applicable to 2-slot configurations.

Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files

Wide fan-in dynamic multiplexers are one of the critical circuits of read-out paths in high-speed register files. However, these dynamic gates have poor noise immunity, which is aggravated by their wide fan-in structure, and their high switching activity consumes significant power. We present new footer voltage feedforward domino (FVFD) and static-switching pulse domino (SSPD) designs for dynamic multiplexers. Both improve noise tolerance, and both reduce the switching power by limiting the voltage swing on the large bitline capacitance through the introduction of dual dynamic nodes. The FVFD technique is based on charge sharing, while SSPD employs a conditional pulse generator to achieve a limited-switching behavior. Adopting these dual dynamic node techniques, we implemented 32-word × 16-bits/word (0.5-Kb) 1-read, 1-write ported register files in a 1.2-V, 65-nm low-VT CMOS process. Although the SSPD and FVFD techniques respectively require 2.4 and 1.4 times more area than the established single-keeper domino technique, comparative analysis through simulations and measurement results suggests that they can be advantageous in terms of both read power and noise immunity.

A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL

Abstract—We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ±2.6% at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively. Index Terms—Digitally controlled oscillator, ring oscillator, PVT compensated DCO, PT-counteracting voltage regulator, all-digital phase-locked loop

Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers

In wide fan-in dynamic multiplexers, the two phase evaluate-precharge operation leads to high switching activity at the dynamic and the output nodes introducing a significant power penalty. To address this issue, the switching-aware design techniques are being explored but these existing techniques suffer from design inflexibilities. In this paper, we propose a pulse domino switching-aware technique, called SSPD, to reduce the overall power consumption of a wide fan-in dynamic gate by having static-like switching behavior at the dynamic node, and the gate input/output terminals. A conditional pulse generator is also proposed, which enables the SSPD multiplexers to be easily adapted to a wide set of noise and delay specifications. Simulation results of 8-bit and 16-bit dynamic multiplexers designed and simulated in a 1.2-V 90-nm CMOS process show that the SSPD technique can reduce the average power by up to 21% and 36%, respectively, when compared to the conventional footless domino technique.

A fast-acquisition PLL using split half-duty sampled feedforward loop filter

We reduce the pattern jitter and acquisition time of a phase-locked loop (PLL) by adopting the split half-duty sampled feedforward loop filter. A prototype designed and fabricated in a 0.18μm standard CMOS technology has a 40% lower acquisition time than a PLL without operating in fast acquisition mode. Its peak-to-peak jitter is 26% less than that of a PLL with a conventional 2nd-order RC loop filter.

A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication

In this paper, we propose a low power transceiver (TRx) suitable for a wired intra-body area network (BAN) communication. The proposed transceiver is designed with relaxation oscillator which is appropriate for this low frequency (< 50MHz) application. To lessen the complexity of building this BAN system, we use clock edge modulation (CEM) data as sending or receiving data, and this allows the transceiver to operate without reference clock. The relaxation oscillator in this transceiver is designed to be able to generate CEM data pattern as well as a clock, so this can minimize power consumption in designing additional block related to transmission. Proposed circuit operates up to 36MHz with 1.0V supply voltage. It consumes 1.26uW at an input data rate of 10Mbps and achieves 0.13pJ/bit of energy per bit even though the circuit is implemented in a 0.18µm CMOS technology.

Phase shift keying demodulator with decision feedback phase-locked loop

This paper proposes a phase shift keying (PSK) demodulator with a decision feedback phase-locked loop. It shrinks the size of capacitor without its performance degrade, compared to that of the conventional PSK phase-locked loop. When a certain threshold is reached by a decision summation, the negative feedback on the loop filters control voltage is provided. Modeled and simulated in VerilogA, the working speed of the proposed circuit is up to 27.12 Mbps, and it can operate for an infinite period of time with the reduced size of the capacitor.

A 1.74mW/GHz 0.11–2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers

A 180° phase-shift digital delay-locked loop (DLL) for LPDDR4 memory controllers is composed of a global DLL and a local DLL for each channel. The global DLL uses a time-to-digital converter to achieve fast-locking, and then shuts down to reduce power consumption. The local DLL, locking based on delay codes from the global DLL, uses a digital window phase detector (PD) and tracks the input clock phase to compensate for process, voltage, and temperature variations. Repeatedly controlled window size of the digital window PD in this local DLL reduces the high-frequency jitter compared to the DLL using bang-bang PD. Implemented in 65nm CMOS process, proposed digital DLL dissipates 1.74mW/GHz and occupies 0.074mm2. It operates over a frequency range of 0.11-2.5GHz, and locks within 6 cycles at 0.11GHz and within 17 cycles at 2.5GHz. At 2.5GHz, the integrated jitter of the DLL output clock with the digital window PD is 953fsrms and the long-term jitter of it is 2.64psrms and 20.6pspp.