Woong Hwan Ryu

6b9b Encoding Scheme for Improving Single-Ended Interface Bandwidth and Reducing Power Consumption without Pin Count Increase

6b9b encoding scheme is proposed to effectively reduces single-ended interconnect. The noise reduction also translates into smaller silicon timing jitter numbers and additional system bandwidth. Moreover, this scheme also reduces active power consumption by 25%.

Controllable parameters identification for high speed channel through signal-power integrity combined analysis

The optimization of high speed channel demands more challenging tasks such as estimating the noise from the interaction between signal nets and power nets, assessing the on-chip power delivery network (PDN) effectiveness, and including the power delivery (PD) to signal coupling noise into the channel budget. However, even just identifying what to optimize in high-speed channel is difficult task, and obtaining meaningful parameters including interaction between signal integrity and power integrity is more challenging. The proposed analysis method employs accurate and more effective ways to find controllable parameters to optimize the channel response for the best performance in the high speed channel considering both signal integrity (SI) and power integrity (PI) interactions by utilizing response decomposition in the time domain with worst case pattern consideration.

Frequency domain topology optimization methodology for a double data rate (DDR) 333 Mbps synchronous DRAM data interface

We propose a novel topology optimization methodology in the frequency domain for a high-speed interface that selects an optimum topology and reduces the time-domain simulation matrix. The method is demonstrated on a DDR333 data interface.

Multi-GHZ modeling and characterization of on-chip power delivery network

On-chip PDN consists of power grid and the intentional decap. In this paper, we demonstrate a technique to determine the on-chip PDN model for a chipset. 2D TLM approach can be used up-to several GHz.

System Level Impact of Stitching Vias and Capacitors for High-Speed Differential Links

This paper discusses the link-level impact and design guidelines of stitching vias and stitching capacitors for highspeed differential systems. Consistent results were obtained between test board VNA/TDR characterization and 3D full-wave EM modeling. While the number and distance of stitching vias and decaps have little or no impact on differential mode crosstalk and ISI, their impact on common-mode crosstalk and ISI is high. Furthermore, effectiveness of stitching capacitors is relatively low at high frequencies comparing to stitching vias. Link-level time domain analysis was also performed to confirm the impact. Finally, a routing guideline for platform design was recommended for stitching vias and capacitors.

SI-PD Co-simulation and Co-design Methodology for High Speed Channel

SI-PD co-modeling, co-simulation, and system response optimization are demonstrated that employ passive modeling of signals and power delivery networks to optimize the system response. Decomposition of the system response and system optimization examples are introduced as well.

Concurrent Analysis of Signal-Power Integrity and EMC for High-Speed Signaling Systems

A robust co-analysis approach for signal integrity, power integrity, and electromagnetic compatibility is successfully established and demonstrated through the investigation of several signal referencing configurations in double data rate (DDR) memory systems. The characterization of power noise coupling into signal channels for two configurations is presented. In addition, a new metric that quantifies the entire signaling system combining simultaneous switching noise and crosstalk is detailed. Finally, the radiated emissions from the power planes in the signalling system are reduced through the proper placement of decoupling capacitors.

Frequency Domain Based Topology Optimization for DRR2-533 DRAM Interface in SFF Domain

This paper discusses signal integrity (SI) challenges in interfacing Intelreg 945 GMS graphics and memory controller hub (GMCH) with DDR2-533 memory (both SO-DIMM and on board memory for SFF (small form factor) designs. SFF designs are constrained by power and space. This paper outlines SI analysis through frequency domain (FD) methodology and correlates with time domain (TD) results. This paper could serve as a guideline with theoretical and implementation details for platform architects and designers. Also it provides the strategic planning and marketing people with an insight on the rising SI challenges faced in interface of high speed and high density memories in SFF designs.