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Dual High-k Gate Dielectric Technology Using Selective AlOx Etch (SAE) Process with Nitrogen and Fluorine Incorporation

We propose a novel Vth, control method for HfSiON (or HfO2) with poly-Si and metal inserted poly-Si stacks (MIPS) gates. By using a selective AlOx etch (SAE) process, we successfully integrate dual high-k gate oxide scheme; HfSiO/poly-Si stack for nMOS and HfSiO/AlOx/poly-Si stack for pMOS. Therefore, symmetrical Vth values of 0.43V(nMOS)/-0.44V (pMOS) have been obtained in poly-Si gate. For MIPS gate, we perform the SAE process with impurity incorporation at the channel region, such as N 2 for nMOS and F for pMOS. Consequently, nMOS Vth of 0.35V and pMOS Vth of -0.45V are obtained without counter channel doping. Moreover, we find out that impurity incorporation at the channel also improves mobility and reliability characteristics. Finally, by using the SAE process with impurity incorporation, maximum operating voltages above 1.0V are obtained by an extrapolated 10 years lifetime

Tunable color emission in a Ba1−xSrxY2S4: Eu2+ phosphor

Abstract X-ray diffraction (XRD) and Photoluminescence (PL) measurements were performed in order to investigate the tunable color emission in a Ba 1− x Sr x Y 2 S 4 : Eu 2+ phosphor. The results of the XRD measurements showed that the Ba 1− x Sr x Y 2 S 4 : Eu 2+ is crystallized with the orthorhombic structure, and those of the PL measurements showed that the PL peak observed in Ba 1− x Sr x Y 2 S 4 : Eu 2+ had a red-shift behavior as a Sr concentration increased. These results indicate that the tuning range of the emission color is approximately between 600 and 640 nm in the Ba 1− x Sr x Y 2 S 4 : Eu 2+ phosphor by changing the Sr composition.

Highly Manufacturable Single Metal Gate Process Using Ultra-Thin Metal Inserted Poly-Si Stack (UT-MIPS)

The authors have successfully developed a mass production friendly single metal gate process utilizing an ultra-thin metal inserted poly-Si stack (UT-MIPS) structure. First, the inserted metal gate thickness effects on device performances are carefully examined, and then the other parameters are optimized to give the best performance. As a results, low and symmetrical short channel Vth (0.44/-0.48 V for n/pMOS) and excellent drive currents (620/230 muA/mum for n/pMOS at Ioff =20pA/mum and Vdd=1.2 V) are obtained without using any mobility enhancement strain technology. The estimated operation voltage for 10 years lifetime of optimized UT-MIPS devices (1.25 V for nMOS PBTI and 1.5 V pMOS NBTI) are well beyond the 1.2 V, showing the good reliability characteristics of UT-MIPS devices as well

Ge Implantation to Improve Crystallinity and Productivity for Solid Phase Epitaxy Prepared by Atomic Mass Unit Cross Contamination-Free Technique

Germanium (Ge) ion implantation was investigated for crystallinity enhancement during solid phase epitaxial (SPE) regrowth. Electron back-scatter diffraction (EBSD) measurement showed numerical increase of 19% of (100) signal, which might be due to the effect of pre-amorphization implantation (PAI) on silicon layer. On the other hand, electrical property such as off-leakage current of n-channel metal oxide semiconductor (NMOS) transistor degraded in specific regions of wafers. It was confirmed that arsenic (As) atoms were incorporated into channel area during Ge ion implantation. Since the equipment for Ge PAI was using several source gases such as BF3 and AsH3, atomic mass unit (AMU) contamination during PAI of Ge with AMU 74 caused the incorporation of As with AMU 75 which resided in arc-chamber and other parts of the equipment. It was effective to use Ge isotope of AMU 72 to suppress AMU contamination. It was effective to use enriched Ge source gas with AMU 72 in order to improve productivity.

Integration Friendly Dual Metal Gate Technology Using Dual Thickness Metal Inserted Poly-Si Stacks (DT-MIPS)

We have successfully developed integration friendly dual metal gate process utilizing a dual thickness metal inserted poly-Si stacks (DT-MIPS) structure; poly-Si/TaN/HfON stacks for nMOS and poly-Si/capping metal layer(c-ML)/AlOx/TaN/HfON stacks for pMOS. First, in spite of different metal thickness on n/pMOS, a high-selectivity gate etch process can completely remove metal and HfON layers from the S/D active regions with negligible Si recess in both n/pMOS. Consequently, in both short and long channel devices, n/pMOS Vth values of ~plusmn0.35 V are obtained without counter channel doping. Moreover, excellent drive currents (620/250 muA/um for n/pMOS at Ioff=20 pA/um and Vdd=1.2 V) are obtained without using any mobility enhancement technique. Finally, we confirm that the estimated operation voltages for 10 years lifetime for both nMOS PBTI and pMOS NBTI are well beyond the 1.2 V.