Seok Woo Nam

PRAM cell technology and characterization in 20nm node size

We reported characteristics of 20nm PRAM cell. Optimization of diode integration process and improved implantation technology were used to satisfy the required diode on-current (Ion) with low off-current (Ioff). Confined cell structure and novel bottom electrode (BE) materials were developed to reduce a reset current (Ireset) below 100uA. Using the advanced technologies, we successfully produced fully integrated 20nm node size PRAM device for the first time.

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

20nm DRAM: A new beginning of another revolution

For the first time, 20nm DRAM has been developed and fabricated successfully without extreme ultraviolet (EUV) lithography using the honeycomb structure (HCS) and the air-spacer technology. The cell capacitance (Cs) can be increased by 21% at the same cell size using a novel low-cost HCS technology with one argon fluoride immersion (ArF-i) lithography layer. The parasitic bit-line (BL) capacitance is reduced by 34% using an air-spacer technology whose breakdown voltage is 30% better than that of conventional technology.

Reliability perspectives for high density PRAM manufacturing

This paper discussed the key reliability issues for manufacturing high density phase change memory (PRAM). There are its own unique phenomena, such as resistance fluctuation, structural relaxation and crystallization, which are closely correlated with the device reliability characteristics, including data retention, cycling endurance, and write disturbance. Optimizing material composition and controlling doping concentration and minimizing variability of physical dimensions can improve the reliability issues. Above all, isotropic dimension scaling along with writing current scaling is essential for continuing scaling down below 20nm node.

Microstructure and corrosion behavior of rapidly solidified Mg-Zn-Y alloys

The effect of a minor change in alloy composition on the microstructure and corrosion properties of melt spun Mg98.3−xZnxY1.7 ribbons with x=9–12 is studied by X-ray diffractometry, differential scanning calorimetry, transmission electron microscopy and a dynamic polarization test. The ribbon specimens with x=9–10 revealed an in-situ composite microstructure consisting of icosahedral quasicrystalline phase (I-phase) particles distributed in an α-Mg matrix. The ribbon specimens with x=11 and 12 contained a minor MgZn2 phase together with an α-Mg phase and I-phase. With increasing Zn content, the corrosion potential increased because of a mixed potential effect, but the formation of a MgZn2 phase deteriorated the corrosion property through preferential attack, causing an irregular boundary between the corrosion product and the substrate. These results indicate that it is important to control alloy chemistry not to form the MgZn2 phase in developing an I-phase strengthened Mg-Zn-Y alloy for structural applications.

Interface control by modified sputtering on Pt/HfO2/Si system

Abstract Hafnium oxide (HfO 2 ) thin films were deposited by two different sputtering methods. In one case, hafnium (Hf) metal layer was pre-deposited before reactive sputtering process (method A), with the object of suppressing growth of the interfacial layer. Another one is conventional reactive sputtering, using DC magnetron in Ar+O 2 ambient (method B). Films made by method A showed thinner interlayer as well as good leakage current behavior, demonstrating that Hf pre-deposited layer can protect from incorporation of the oxidizing species. With high-temperature annealing, interfacial layer increases considerably, showing composition changes from silicate to SiO 2 (method A). In contrast, films by method B displayed little change in interlayer thickness since there exists previously thick SiO x bottom layer formed by O 2 stabilizing before reactive sputtering. Equivalent oxide thickness (EOT) of as-deposited and annealed HfO 2 films by method A is calculated to be ∼20 and ∼30 A, respectively, with allowable level of leakage current density.

Electric field effect dominated bipolar resistive switching through interface control in a Pt/TiO2/TiN structure

To investigate the reproducibility and I–V non-linearity characteristics in resistive-switching random-access memory (RRAM), we studied the switching characteristics through Pt/TiO2 interface control using a non-stoichiometric TiO2−x/TiN interface formation in a resistive switching Pt/TiO2/TiN stack. Using the TiO2−x/TiN interface instead of the TiO2/TiN interface induced nearly forming-free switching, decreased the reset current, suppressed the gradual reset process, and resulted in faster switching by electric pulse. These results indicate that the Pt/TiO2 interface experienced reduced oxygen-vacancy-mediated switching. The discrepancy between the reduced oxygen-vacancy-mediated switching and the initially large number of oxygen vacancies can be resolved via the oxygen vacancy distribution dependent field effect. To clarify this process, we performed reaction-diffusion-drift model simulations. The drift velocity, which was calculated using the vacancy distribution, described the dynamic movement, and the simulation results supported the experimentally observed faster switching response. The field effect, which provided successive feedback between the drift velocity and vacancy distribution, can potentially be exploited to generate vacancy-designed devices.

Considerations on highly scalable and easily stackable phase change memory cell array for low-cost and high-performance applications

Needs for the performance improvement of memory subsystem in big data and clouding computing era begin to open new markets for emerging memories such as phase change memory, spin-torque-transfer magnetic memory, and metal oxide memory. To fulfill these needs, a cost-effective and high-speed phase change memory cell scheme was introduced at 19nm technology node, which is directly scalable down to 1y or 1z nm nodes and can be extendable to stacked array for higher density. Here, key technologies such as self-aligned cell patterning and vertical poly-Si diode switch on metal word line were adopted. In addition, damascene Ge-Sb-Te technologies were optimized to improve programming speed and to show excellent cell performances.

Novel flowable CVD process technology for sub-20nm interlayer dielectrics

Flowable CVD (Chemical Vapor Deposition) process having merits in terms of both superior gap-fill performance of SOD (Spin-on Dielectric) and process stability of CVD was introduced for the interlayer dielectric (ILD) in sub-20nm devices based on new concept and precursor. Remote plasma during low temperature deposition and ozone treatment was adopted to stabilize the film. We also developed a novel Flowable CVD process which does not oxidize Si or electrode, resulted in removal of Si3N4 stopper layer as an oxidation or diffusion barrier. After the application of Flowable CVD to 20nm DRAM ILD, we could reduce not only loading capacitance of Bit-line by 15% but also enhance comparable productivity. Through the successful development of sub-20nm DRAM ILD Gap-fill process, Flowable CVD was successful demonstrated as a promising candidate for mass production-worthy ILD in sub-20nm next generation devices.

Evaluation of the electrical properties and interfacial reactions for the polycrystalline Si1−xGex(x=0,0.6)/HfO2 gate stack

The effect of interfacial reactions on the electrical properties of a polycrystalline (poly) Si1−xGex/HfO2 gate stack were evaluated in terms of annealing conditions and the results were compared with those of a conventional poly-Si/HfO2 system. In the poly-Si0.4Ge0.6/HfO2 gate stack, silicate formation was the dominant reaction at the poly-Si0.4Ge0.6/HfO2 interface after annealing at 900 °C, resulting in the significant decrease in leakage current. From x-ray photoelectron spectroscopy analysis, the binding states of Hf silicates were clearly observed at a binding energy of about 16.1 eV in Hf 4f spectra and 102.7 eV in Si 2p spectra. However, in the poly-Si/HfO2 gate stack, the accumulation capacitance became undeterminable and the leakage current increased suddenly after annealing at 900 °C due to silicide formation at the poly-Si/HfO2 interface. The differences in reactions between a poly-Si/HfO2 interface and a poly-Si0.4Ge0.6/HfO2 interface are attributed to the accumulation of Ge.