Woong Sun Lee

Reliability issues on the high speed DRAM flip-chip package using gold stud bump, lead free solder, and underfill

In this study, flip-chip packaging method was using gold stud bump on chip side and SnAgCu, lead free solder pad on organic substrate. Also capillary underfill enhanced the mechanical properties of gold-solder bump joint. This method was set up to the mass production of the high speed DRAM (Dynamic Random Access Memory) flip-chip package. This kind of gold stud flip-chip package has some weak points on mass production and package reliability. To discover the weak point on mass production and reliability of package, the microstructure of the flip-chip gold-stud and solder bump joints were studied. Gold-tin intermetallics were formed on whole bump joint body after flip-chip packaged as many researchers reported. The delta, epsiv, and eta-gold-tin intermetallic compounds formed sequentially from the gold stud bump. Reflow, high temperature and high humidity (85degC/85%), and pressure cooker test (PCT) method were used to study the reliability of this gold stud and solder flip-chip package. From this reliability test, the coverage of solder to the gold bump was very important point of the reliability issue. In flip-chip bonding process, the variations of bonding parameter affected the length of the gold stud and solder joint. In case of the solder covered the whole gold bump body, this package was failed perfectly in PCT test. From the warpage data of the package after reliability tested and through the stress analysis, the gold-solder intermetallic and humidity made the crack initiator in the root area of gold stud bump. Thermal simulation was performed to prevent this solder coverage over the whole body of gold stud bumps. Also, combinations of underfill and solder resist material on the substrate affected the PCT test results. We chosen 3 types of underfill from A company and 4 types of solder resist material from B company. 2 mm by 2 mm silicon nitride test coupon attached with various underfill on substrate processed with various solder resist material. Those test vehicles were tested with shear test after 240 hrs PCT. Underfill and solder resist material had a common base polymer, epoxy but test results showed different results from different combinations. Substrate makers chosen solder resist materials which had good development characteristics in their patterning process because the flip-chip package had very complicated input/outputs on its surface. But it is very important to consider the compatibilities of processing and reliability aspects between underfill and solder resist.

The availability of the thermal resistance model in flip-chip packages

Thermal resistance model is very simple and good tool for thermal analysis of package system. In this study, thermal resistance model was compared with simulation tool and real measurement values of flip-chip package which was made by using DTSA (Diode Temperature Sensor Array). Especially, a micro thermocouple sensor array - DTSA - has been developed to investigate the temperature distributions of underfill in flip-chip package. Various fillers were used with underfill resin system, silica, diamond, and alumina. The temperature distribution of flip- chip package was changed with various underfill system. ICEPAK simulation tool predicted the change of temperature distribution of package well and using same physical dimension, we made a thermal resistance model circuit and calculated thermal resistance values with various underfill systems thermal conductivity values which were measured with the laser flash method. Finally, measured values with DTSA was compared with ICEPAK simulated values and thermal resistance model. All three different methods thermal resistance values of maximum temperature were lay 20degC/W ~ 25degC/W. Thermal resistance model predicted the thermal resistance of DTSA flip-chip package well.

Reliability enhancement of embedded capacitors in printed circuit boards using B-stage epoxy/BaTiO 3 composite embedded capacitor films (ECFs)

Epoxy/ceramic composites are one of promising materials as embedded capacitors for a SiP technology, because they have a good processability and a compatibility with printed circuit boards (PCBs), in addition to a high dielectric constant. In this study, we have fabricated embedded capacitors in PCBs using epoxy/BaTiO3 ECFs, and evaluated their reliability at high temperature aging after moisture absorption. Factors influencing the reliability of epoxy/BaTiO3 ECF capacitors were analyzed in terms of materials formulation, the ratio of epoxy and BaTiO3, dispersant contents, and curing agent. From these results, epoxy/BaTiO3 ECFs materials were optimized in terms of reliability and dielectric properties. And, using these optimized epoxy/BaTiO3 ECFs, embedded capacitors in prototype-scale, 405 × 508 mm, PCBs were fabricated by conventional multi-layer PCB build-up processes. The total thickness of PCB including embedded capacitors was below 250 µm. And their reliability at high temperature aging after moisture absorption was well qualified.