Woorham Bae

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weightadjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-㎚ CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9?28 inch Nelco4000-6 microstrips at 4?7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 ㎟ and consumes 69.8 ㎽, while the rest of the receiver occupies 0.297 ㎟ and consumes 56.0 ㎽ at the 7-Gb/s data-rate and supply voltage of 1.35 V.

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

This paper presents a 22 to 26.5 Gb/s optical receiver with an all-digital clock and data recovery (AD-CDR) fabricated in a 65 nm CMOS process. The receiver consists of an optical front-end and a half-rate bang-bang clock and data recovery circuit. The optical front-end achieves low power consumption by using inverter-based amplifiers and realizes sufficient bandwidth by applying several bandwidth extension techniques. In addition, in order to minimize additional jitter at the front-end, not only magnitude and bandwidth but also group-delay responses are considered. The AD-CDR employs an LC quadrature digitally controlled oscillator (LC-QDCO) to achieve a high phase noise figure-of-merit at tens of gigahertz. The recovered clock jitter is 1.28 ps rms and the measured jitter tolerance exceeds the tolerance mask specified in IEEE 802.3ba. The receiver sensitivity is 106 and 184 for a bit error rate of 10-12 at data rates of 25 and 26.5 Gb/s, respectively. The entire receiver chip occupies an active die area of 0.75 mm2 and consumes 254 mW at a data rate of 26.5 Gb/s. The energy efficiencies of the front-end and entire receiver at 26.5 Gb/s are 1.35 and 9.58 pJ/bit, respectively.

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverter-based frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed 10 GHz PLL fabricated in the 65 nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB.

A power-efficient 600-mVpp voltage-mode driver with independently matched pull-up and pull-down impedances

SUMMARY In this study, a large-swing, low-power voltage-mode driver with independently matched pull-up and pull-down impedances is proposed. To achieve large swing and constant impedances during a transition, a P-over-N structure is implemented with regulators calibrating the impedances. Two regulators are dedicated to matching the pull-up and pull-down impedances by regulating the supply voltages of the driver and predriver, respectively. Because background impedance calibration loops are adopted to track the process, voltage, and temperature (PVT) variations, the proposed driver can operate properly without additional calibration time. To reduce the power consumption of the calibration loops, scaled replicas of the actual driver are used. Moreover, an analysis of design optimization for the proposed driver is presented. The proposed driver was fabricated in 65-nm CMOS technology and verified at a 5-Gb/s data rate. Measurement results show that the proposed driver has a voltage swing of 600 mVpp and a horizontal eye opening of 0.5 UI. The prototype chip consumes 6 mW at a 1.0-V supply. Copyright

A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL

Abstract—We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ±2.6% at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively. Index Terms—Digitally controlled oscillator, ring oscillator, PVT compensated DCO, PT-counteracting voltage regulator, all-digital phase-locked loop

A 0.36 pJ/bit, 0.025 mm 2 , 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.

This paper describes a power and area-efficient forwarded-clock (FC) receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a delay-locked loop (DLL) based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-UIpp sinusoidal jitter of 300 MHz.

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm2. Due to the wide jitter tracking bandwidth of DLL and the inherent jitter correlation between data and forwarded clock, the proposed receiver exhibits outstanding jitter tolerance whose corner frequency is higher than 300 MHz.

A crossbar resistance switching memory readout scheme with sneak current cancellation based on a two-port current-mode sensing

This paper describes a novel readout scheme that enables the complete cancellation of sneak currents in resistive switching random-access memory (RRAM) crossbar array. The current-mode readout is employed in the proposed readout, and a few critical advantages of the current-mode readout for crossbar RRAM are elucidated in this paper. The proposed scheme is based on a floating readout scheme for low power consumption, and one more sensing port is introduced using an additional reference word line. From the additional port, information on the sneak current amount is collected, and simple current-mode arithmetic operations are implemented to cancel out the sneak current from the sensing current. In addition, a simple method of handling the overestimated-sneak-current issue is described. The proposed scheme is verified using HSPICE simulation. Moreover, an example of a current-mode sense amplifier realizing the proposed cancelling technique is presented. The proposed sense amplifier can be implemented with less hardware overhead compared to the previous works.

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant-

This paper describes a transmitter driver based on a CMOS inverter with a resistive feedback. By employing the proposed driver topology, the pre-driver can be greatly simplified, resulting in a remarkable reduction of the overall driver power consumption. It also offers another advantage that the implementation of equalization is straightforward, compared with a conventional voltage-mode driver. Furthermore, the output impedance remains relatively constant while the data is being transmitted, resulting in good signal integrity. For evaluation of the driver performance, a fully functional 20 Gb/s transmitter is implemented, including a PRBS generator, a serializer, and a half-rate clock generator. In order to enhance the overall speed of the digital circuits for 20 Gb/s data transmission, the resistive feedback is applied to the time-critical inverters, which enables shorter rise/fall times. The prototype chip is fabricated in a 65 nm CMOS technology. The implemented driver circuit operates up to the data rate of 20 Gb/s, exhibiting an energy efficiency of 0.4 pJ/b for the output swing of 250 mVpp,diff.

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A 10 Gb/s PLL-based forwarded clock receiver is implemented in 65-nm CMOS technology. The proposed architecture uses a hybrid PLL-based deskew which is combined with a PLL and a DLL. The PLL provides jitter filtering and the DLL performs deskewing by shifting the divided clocks. Since the operating frequency of the DLL is low, the power consumption of the DLL can be reduced. The measurement results show that the rms jitter of the recovered clock is only 576.7 fs which is quite low for a ring-oscillator-based PLL. The receiver chip occupies an active area of 0.0136 mm2 and consumes 22.1 mW at the data rate of 10 Gb/s.