Haram Ju

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverter-based frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed 10 GHz PLL fabricated in the 65 nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB.

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant-

This paper describes a transmitter driver based on a CMOS inverter with a resistive feedback. By employing the proposed driver topology, the pre-driver can be greatly simplified, resulting in a remarkable reduction of the overall driver power consumption. It also offers another advantage that the implementation of equalization is straightforward, compared with a conventional voltage-mode driver. Furthermore, the output impedance remains relatively constant while the data is being transmitted, resulting in good signal integrity. For evaluation of the driver performance, a fully functional 20 Gb/s transmitter is implemented, including a PRBS generator, a serializer, and a half-rate clock generator. In order to enhance the overall speed of the digital circuits for 20 Gb/s data transmission, the resistive feedback is applied to the time-critical inverters, which enables shorter rise/fall times. The prototype chip is fabricated in a 65 nm CMOS technology. The implemented driver circuit operates up to the data rate of 20 Gb/s, exhibiting an energy efficiency of 0.4 pJ/b for the output swing of 250 mVpp,diff.

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A 10 Gb/s PLL-based forwarded clock receiver is implemented in 65-nm CMOS technology. The proposed architecture uses a hybrid PLL-based deskew which is combined with a PLL and a DLL. The PLL provides jitter filtering and the DLL performs deskewing by shifting the divided clocks. Since the operating frequency of the DLL is low, the power consumption of the DLL can be reduced. The measurement results show that the rms jitter of the recovered clock is only 576.7 fs which is quite low for a ring-oscillator-based PLL. The receiver chip occupies an active area of 0.0136 mm2 and consumes 22.1 mW at the data rate of 10 Gb/s.

Bias

This paper presents an energy-efficient transmitter driver architecture that is suitable for high-speed operation. By employing an inverter with resistive feedback as a driver cell, the proposed driver topology can overcome the disadvantage of conventional voltage-mode drivers, namely, that the pre-driver power consumption increases as the data rate increases. This driver topology has another advantage that equalization can be easily realized. In order to evaluate the performance of the proposed driver, a PRBS generator, a serializer, and a half-rate clock generator are included in the prototype chip. The proposed driver and equalizer circuit operate reliably at a data rate of up to 20 Gb/s exhibiting an energy efficiency of 0.4 pJ/b for an output swing of 250 mVppd.

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS

In order to suppress the malfunction caused by the shift of the threshold voltage (VTH) of oxide thin film transistors (TFTs) to a negative value, double-gate TFTs are used in the shift register of the gate driving system to control VTH by adjusting the top gate bias. The proposed circuit detects the current consumption of the shift register and adjusts VTH so that the current consumption of the shift register is regulated within the desired value. The system includes a compensation algorithm, which can search for an optimized top gate bias in various circumstances such as process fluctuations and ambient temperature change. The proposed system provides a stable operation compared with a conventional structure especially at high temperature. Experimental results show that, in the conventional system without compensation, the output voltage of the shift register deteriorates at 80°C and above, and the power consumption increases from 1.15 to 2.14 mW after 21600 s of continuous operation at 60°C. On the other hand, the proposed system provides a stable gate output up to 100°C and keeps the power consumption below 1.10 mW by adjusting the top gate bias responding to environment changes.

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm

This paper presents a -245.3 dB FoMJ phase-locked loop based on a ring oscillator and a novel analysis on 2-stage ring oscillator. The proposed PLL generates a 4-phase 10-GHz clock for a 40-Gb/s serial link transmitter. The proposed analysis offers a time-domain insight on 2-stage ring oscillator and a precise prediction on oscillator behavior such as an output frequency and whether the 2-stage ring oscillates or not, based on a simple open-loop approach with a single stage buffer. The prototype chip is fabricated in 65-nm CMOS technology, and the PLL occupies only 0.009 mm2 and dissipates 7.6 mW from 1.2-V supply and 9 mW from 1.3-V supply. The measured integrated jitter of the PLL is 214 fs from 1.2-V supply and 182 fs from 1.3-V supply, which corresponds to -244.6 dB and -245.3 dB FoMJ, respectively.

Real-Time External Compensation of Threshold Voltage Shift Using Double-Gate Oxide TFTs in a Gate Driving System

We presents an energy-efficient PAM-4 transmitter that provides a controlled output impedance, scalable output voltage swing, and fractionally spaced feed-forward equalization (FFE). By using a resistive-feedback output driver, the proposed PAM-4 transmitter can reduce the power dissipation in the pre-driver stages compared with conventional transmitters. It also offers a more straightforward implementation of a 3-tap FFE owing to the simple current-summing structure of the pre-driver. In addition, the output impedance of the proposed output driver is controlled by regulating the

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS

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A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and

of the driver cell, which results in good signal integrity for high-speed operation without the use of peaking inductors. A prototype chip is fabricated in 28-nm CMOS technology and occupies an active area of 0.048 mm2. It achieves a data rate of 28 Gb/s, exhibiting the state-of-the-art energy efficiency of 1.59 pJ/b for the differential output swing of 207 mV.

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A 800-Mb/s optical receiver based on pulse-position-modulation (PPM) scheme is presented. The proposed PPM receiver can recover the clock without any help of a reference clock or a forwarded clock. As a result, the number of wire and pin count is minimized. Moreover, the proposed receiver employs optical front-end circuits for fiber-optic communications which is optimized for low-power operation. The clock and data recovery (CDR) circuit is implemented with only a PLL and a sampling flip-flop to minimize the power consumption of the proposed receiver. A prototype chip is fabricated in 65-nm CMOS technology and dissipate s 711 μW at 800-Mb/s data rate, achieving the power efficiency of 0.89 pJ/b. The measured jitter tracking bandwidth of the prop osed receiver is about 10 MHz and the receiver sensitivity is measured to be -9.7 dBm for the BER of 10-12.