Wu Dexin

Extrinsic Base Surface Passivation in High Speed “Type-II" GaAsSb/InP DHBTs Using an InGaAsP Ledge Structure

Type-II GaAsSb/InP DHBTs with selectively-etched InGaAsP ledge structures are fabricated and characterized for the first time. The novel InGaAsP/GaAsSb/InP DHBTs with a 20 nm lattice-matched GaAsSb base and a 75 nm InP collector have a dc current gain improvement by a factor of 2 and a cutoff frequency fT of 190 GHz. The InGaAsP ledge design provides a simple but effective approach to suppress the extrinsic base surface recombination and enable GaAsSb/InP DHBTs to further increase the operating frequencies and integration levels for millimeter wave applications.

Minimize dishing effects during chemical mechanical planarization of copper damascene structures

Copper CMP is one of the key steps in the damascene process. Some experiments on of Copper CMP were done based on the homemade CMP machine and the novel FA/O Cu slurry made in China. The mechanism of Copper CMP using the novel slurry was given. The dishing effects during Cu CMP were discussed in detail. Furthermore, the dishing effect was minimized by adjusting the applied pressure.

One-dimensional non-contact PSD with high performance

A one-dimensional noncontact Position Sensing Detector (PSD) with a new type structure has been investigated. The structure is different from that of the conventional PSD. Experiments show that the detector has a high degree of linearity and high sensitivity. Typical test results of our 1/spl times/6 mm/sup 2/ PSD device are: position resolution (minimum light spot displacement that can be detected) is extremely good and has been proven to be 3/spl times/10/sup -7/ m; response time /spl tau//sub r/ is about 10 /spl mu/s; photoelectric sensitivity is as high as 0.45 A/W; dark current of the device is about 10/sup -9/ A and the device has a high degree of linearity within the spectrum range from 720 nm to 1190 nm. Also, the fabrication processes and working circuit of the device are described.

Quantum resonant tunneling effect and multi-value logic memory

A novel fabrication process, based on selective wet etching and GaAs air-bridge was developed to produce AlAs/GaAs, AlAs/InAs/GaAs quantum dots double barrier quantum well sub-micron resonant tunneling diodes (RTD), and the peak to valley current ratio could be over 20. A new model of multilevel logic SRAM with RTDs was proposed.

High-Quality Single Crystalline Ge(111) Growth on Si(111) Substrates by Solid Phase Epitaxy

Heterogeneous integration of crystalline Ge layers on cleaned and H-terminated Si(111) substrates are demonstrated by employing a combination of e-beam evaporation and solid phase epitaxy techniques. High-quality single crystalline Ge(111) layers on Si(111) substrates with a smooth Ge surface and an abrupt interface between Ge and Si are obtained. An XRD rocking curve scan of the Ge(111) diffraction peak shows a FWHM of only 260 arcsec for a 50-nm-thick Ge layer annealed at 600°C with a ramp-up rate of 20°C/s and a holding time of 1 min. The AFM images exhibit that the rms surface roughness of all the crystalline Ge layers are less than 2.1 nm.

Fully-depleted SOI NMOS transistors with p/sup +/-polysilicon gate

p/sup +/ polysilicon and n/sup +/ polysilicon were used as the gate material for fully-depleted SOI NMOS transistors. Its found that n-channel transistors with p+ poly gates require lower channel doping levels than their n/sup +/ poly counterparts, leading to easier formation of depleted film and control of the threshold voltage. The low channel doping results in improved source-drain breakdown characteristic.

Analytical threshold voltage model for ultrathin SOI MOSFET's

The threshold voltage of fully depleted silicon-on-insulator (SOI) MOSFET with channel lengths down to the deep-submicrometer range has been investigated. By applying Gausss law, a quasi-two-dimensional analytical threshold voltage model for ultra-thin SOI fully depleted MOSFETs including the short-channel effect (SCE) is achieved. Furthermore, we consider further the threshold voltage of FDSOI MOSFET and in particular the value of the surface potential at threshold. It is shown that the surface potential at FDSOI MOSFET threshold may differ significantly from 2 /spl phi/ i. We extend this model by accounting for surface potential about P+ poly-silicon gate, a closed form expression for the threshold voltage is obtained and compared with experimental data for several SOI FD MOSFETs.

Study on key technologies of copper metallization in ULSI

In this paper we discuss the current damasense processes of copper metallization. The study will be focus on some key technologies such as novel barrier, copper deposition and chemical mechanical polishing (CMP) processes.

An advanced structural deep-submicron MOS device

An advanced structural deep sub-micron MOS device was presented and fabricated based on conventional photolithography equipment and novel side-wall technique. The effective channel length of 0.2 /spl mu/m could be reached. The transconductances of the optimized devices were 125 and 80 mS/mm for n-MOSFET and p-MOSFET respectively. The breakthrough voltages were 10 and 11 volt respectively for n-MOSFET and p-MOSFET.