Hai Chao-he

Total dose radiation experiments in CMOS/SOI 4 Kb SRAM

This paper describes the total dose radiation performance of CMOS/SOI 4 Kb SRAMs fabricated in a radiation hardened partially depleted SOI CMOS technology. The SRAM adopts 1 K/spl times/4 architecture. It achieves a fast access time 30 ns and chip size 3.6 mm/spl times/3.84 mm. Memory functionality does well after a total dose irradiation up to 5/spl times/10/sup 5/ rad(Si) under 3 V power supply. This meets the needs in military and aerospace fields. It is the first time that the radiation effects on SOI VLSI were investigated in China.

Model Parameters Extraction of SOI MOSFETs

Device model parameters extraction is often performed using commercial software. But the software is usually not efficient for SOI MOSFETs because of their limitation. In this paper, the genetic algorithm is improved through combining with simulated annealing algorithm. The improved algorithm is used to extract model parameters of SOI MOSFETs, which are fabricated by standard 1.2 mum CMOS/SOI technology developed by Institute of Microelectronics of Chinese Academy of Sciences. The simulation result using this model is in excellent agreement with the experimental result. The precision is improved evidently compared with commercial software. This method requires neither deep understanding of SOI MOSFETs model nor complex computation compared with conventional methods used by commercial software. Comprehensive verification shows that this model is applicable to a very large region of device sizes

Study on the dose rate upset effect of partially depleted silicon-on-insulator static random access memory

This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM (Partially Depleted Silicon-On-Insulator Static Random Access Memory) with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM (Static Random Access Memory) chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. A specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about 1×108 Gy(Si)/s. However, there are a few bits upset when the dose rate reaches up to 1.58 × 109 Gy(Si)/s. The SRAM circuit can still work after the high level γ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations are made to improve the dose rate hardened performance of the PDSOI SRAM.

Fully-depleted SOI NMOS transistors with p/sup +/-polysilicon gate

p/sup +/ polysilicon and n/sup +/ polysilicon were used as the gate material for fully-depleted SOI NMOS transistors. Its found that n-channel transistors with p+ poly gates require lower channel doping levels than their n/sup +/ poly counterparts, leading to easier formation of depleted film and control of the threshold voltage. The low channel doping results in improved source-drain breakdown characteristic.