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Featured researches published by Wu Sun.


ISTC/CSTIC 2009 (CISTC) | 2009

Yield Enhancement with Optimized Offset Spacer Etch for 65nm Logic Low-leakage Process

Baodong Han; Shih-Mou Chang; Haiyang Zhang; Linlin Zhao; Yali Fu; Wu Sun; Bing-Wu Liu

This paper presents an effective way to reduce the degradation of the Ring-OSC speed with optimized offset spacer etch, improvement of the within-wafer uniformity of the offset spacer width and the reduction of its profile deviation. We have developed the lower offset spacer etch rate scheme for better control of plasma uniformity in order to achieve the above two targets. Compared with the 3Sigma of 1.3nm offset spacer width uniformity and 1.8nm profile deviation of conventional dielectric etcher with high etch rate, this low etch rate process has delivered the 3sigma of 0.5nm for the offset spacer width uniformity and 0.7nm offset spacer profile deviation. The corresponding Ring-OSC loss has been completely eliminated and the wafer-level yield is enhanced by 40%.


ISTC/CSTIC 2009 (CISTC) | 2009

Etch Arts of Dual Damascus Structure and Their Impacts on WAT/VBD in 65nm Cu Interconnects

Wu Sun; Shih-Mou Chang; Haiyang Zhang; Xiaoming Yin; Liya Fu; Baodong Han; Xinpeng Wang; Yongqin Wu

In this paper, based on the via-first DD technology, we focus on the profile tuning of via and trench and the liner removal in order to optimize the trench profile. Via profile tuning include how to realize the via with the bowling profile, vertical profile and tapering profile. Trench profile tuning emphasizes the formation mechanism of bowling profile and top rounding profile. Footing profile and under-cutting profile of via bottom in liner open step is also addressed. The effect of different etching profiles on Rc, VBD (Breakdown Voltage) are examined. Results show that different via profiles have no impact on Rc, top-rounding trench-profile results in worse VBD, while under-cut & footing liner would deliver lower and higher Rc, respectively.


international conference on solid-state and integrated circuits technology | 2008

Mechanism of via etch striation and its impact on contact resistance & breakdown voltage in 65nm cu low-k interconnects

Wu Sun; Manhua Shen; Xinpeng Wang; Haiyang Zhang; Xiaoming Yin; Shih-Mou Chang

The mechanism of two kinds of via etch striation (type I and type II) has been investigated to improve contact resistance (Rc) uniformity and solve breakdown voltage (VBD) issue in 65 nm Cu low-k interconnects. Heavy etching polymer deposition on the sidewall of capping layer and rapid photo-resist (PR) consumption on PR shoulder are two main resources to result in via etch striation. The effects of both via etch striations on Rc and VBD can be decoupled. Type I striation related to barc open (BO) step leads to worse Rc uniformity while type II striation formed in main etch (ME) and over-etch (OE) step degrades VBD performance.


Archive | 2009

Through-hole forming method

Manhua Shen; Xinpeng Wang; Ping Liu; Wu Sun


Archive | 2014

Manufacture method for semiconductor device

Wu Sun; Xiaoming Yin; Haiyang Zhang; Yongqin Wu


Archive | 2012

Method for forming dual mosaic structure

Manhua Shen; Wu Sun; Xiaoming Yin


Archive | 2012

Forming method of welding pad structure

Xinpeng Wang; Manhua Shen; Wu Sun; Shimou Zhang


Archive | 2011

Connection pore forming method

Manhua Shen; Wu Sun; Xinpeng Wang


Archive | 2011

Semiconductor element for use in interconnection process and manufacturing method thereof

Wu Sun; Haiyang Zhang; Xinpeng Wang; Qiang Xu


Archive | 2009

Forming method of under pump metal layer and connecting cushion

Xinpeng Wang; Qiuhua Han; Manhua Shen; Wu Sun

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Haiyang Zhang

Semiconductor Manufacturing International Corporation

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Yi Huang

University of Southampton

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Junqing Zhou

Semiconductor Manufacturing International Corporation

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Min-Da Hu

Semiconductor Manufacturing International Corporation

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Xing-Hua Song

Semiconductor Manufacturing International Corporation

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