Xabier Iturbe

A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs

This paper presents a new Single Event Upset (SEU), Multiple Bit Upset (MBU) and Single Hardware Error (SHE) mitigation strategy to be used in Virtex-4 FPGAs. This strategy aims to increase not only the effectiveness of traditional TripleModule Redundancy (TMR), but also the overall system availability. Frame readback with ECC detection and frame scrubbing are combined in a dynamically reconfigurable TMR architecture, designed under both spatial and implementation diversification premises. Moreover, since the strategy works on the devices bitstream domain, the basis for Virtex-4 FPGAs bitstream definition are also shown.

R3TOS: A reliable reconfigurable real-time operating system

The foundations for building the first Reliable Reconfigurable Real-Time Operating System (R3TOS) are presented. The main objective of R3TOS is to create an infrastructure for coordinately executing specialized hardware tasks upon a reconfigurable FPGA device, achieving the necessary flexibility for both gaining system performance (true hardware multitasking) and tolerating the occurring faults in the underlying chips silicon at runtime (true fault removal from system). R3TOS is aimed at easing the development of FPGA-based high-performance demanding reliable applications by hiding the complexity of these devices, promoting their use by the whole engineering community.

Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs

This paper presents the details of a novel technique which allows for the implementation and execution of completely relocatable hardware tasks onto dynamically reconfigurable FPGAs. Our novel technique harnesses the internal configuration access port (ICAP) for inter-task communication and synchronization, leading to very little logic overheads. The advantages of this technique include fault-tolerance, as tasks could be relocated freely on the fabric to circumvent damaged resources, and high performance, due to better exploitation of the logic fabric. The work is part of a larger effort in our group which aims to build a fully operational dynamically reconfigurable computer which would satisfy the often conflicting requirements of high performance, fault-tolerance and high level programming.

A Roadmap for Autonomous Fault-Tolerant Systems

An Autonomous Fault-Tolerant System (AFTS) refers to a system that is able to configure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain its functionality. This work analyzes how AFTS could be built, specifically focusing on hardware platform dependant issues, and gives an overview of the state-of-the-art in this field, which is still in its infancy. Three technological levels are used for classifying the research efforts conducted to date. By describing the current state-of-the-art and the constraints imposed by current technology, this work tries to envision future trends towards the ultimate objective of achieving a fully-adaptive system capable of modifying its architecture on-the-fly as needed. Finally, the general structure and organization of a Reliable Reconfigurable Real-Time Operating System (R3TOS) is presented. This OS aims at making the aforementioned adaptability easily exploitable by future commercial applications.

Efficient On-Chip Task Scheduler and Allocator for Reconfigurable Operating Systems

This letter presents efficient and modular task scheduler and allocator support for dynamically and partially reconfigurable electronic systems. This enables hardware tasks to be preempted and arbitrarily placed at an optimal position on the chip on-the-fly. In particular, we present a novel fault-tolerant allocating algorithm called “best-fit empty area compact (BF-EAC),” and its on-chip implementation on a Xilinx Virtex-4 field-programmable gate array (FPGA), which circumvents emerging faults while maintaining more compact empty areas for emerging tasks. We also present an implementation of the early deadline first (EDF) scheduling heuristic used to optimize the chronological order of execution of hardware tasks to meet real time constraints. Put together, the placement and scheduling architecture efficiently exploits chip resources with a μs-grade computing speed and a lightweight footprint (less than 500 slices).

Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail in this article. These algorithms consider most of the technological constraints existing in modern partially reconfigurable FPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition, the algorithms target other important aspects such as communications and synchronization among the different computations that are carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide range of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined.

Empty Resource Compaction Algorithms for Real-Time Hardware Tasks Placement on Partially Reconfigurable FPGAs Subject to Fault Ocurrence

This paper deals with online scheduling and allocation of real-time hardware tasks onto partially reconfigurable Xilinx FPGAS. We present a novel fault-aware online allocator which ensures the correctness of the computation by circumventing the permanent damage in the chip. The allocator is merged with an EDF-based scheduler to make up a highly-Reliable Reconfigurable Real-Time Operating System (R3TOS). The experiments carried out show that R3TOS misses 10% less deadlines and reduces the scheduling time overhead by over 90% compared with related approaches.

R3TOS-Based Autonomous Fault-Tolerant Systems

An autonomous fault-tolerant system (AFTS) is one that can reconfigure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain the original functionality. This capability makes an AFTS especially suitable for use in harsh environments, where traditional electronics technology is susceptible to failure. This article describes the contributions of the Reliable Reconfigurable Real-Time Operating System (R3TOS) for building an AFTS using currently available Xilinx partially-reconfigurable field-programmable gate arrays. Namely, this article discusses what R3TOS offers for developing durable, dependable, and real-time embedded systems to be used in rugged environments. In this context, the article presents an R3TOS-based inverter controller of a real-world railway traction system that is proven to recover from most of the errors injected without requiring any human intervention.

Enabling FPGAs for future deep space exploration missions: Improving fault-tolerance and computation density with R3TOS

Future deep space exploration missions will require small, lightweight, low-power, fault-tolerant, autonomous and durable onboard electronic systems. In this paper we present R3TOS, a novel approach for online scheduling and allocating different pieces of circuitry onto partially reconfigurable FPGAs to match the specific computation needs at all times. R3TOS targets two main objectives: (i) obtain the best performance per unit of devices area and per unit of consumed energy and, (ii) minimize the impact of devices degradation on performance.

On enhancing the reliability of internal configuration controllers in FPGAs

In fault-tolerant FPGA systems, the internal reconfiguration capabilities supported in modern FPGAs is commonly utilized for enhanced fault mitigation. In such systems, faults in the internal configuration controller can degrade the fault-tolerance of the system and in extreme cases can lead to additional faults injected into the system. In this paper we present different methods for enhancing the reliability of internal configuration controllers in FPGAs. We demonstrate the design of a custom ICAP controller for Xilinx Virtex FPGAs and compare the reliability and area overhead for Triple Modular Redundancy (TMR), Dual Modular Redundancy (DMR) and Cyclic Redundancy Check (CRC) design schemes. We also evaluate the effectiveness of internal readback and external configuration memory scrubbing and show how a combination of the two methods can reduce the number of single points of failure in the system.