Xiabing Lou

Atomic layer deposition of Sc2O3 for passivating AlGaN/GaN high electron mobility transistor devices

Polycrystalline, partially epitaxial Sc2O3 films were grown on AlGaN/GaN substrates by atomic layer deposition (ALD). With this ALD Sc2O3 film as the insulator layer, the Sc2O3/AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors showed excellent electrical performance with a high Ion/Ioff ratio of over 108 and a low subthreshold slope of 75 mV/dec. The UV/NH4OH surface treatment on AlGaN/GaN prior to ALD was found to be critical for achieving these excellent figures. In addition, the Sc2O3 dielectric is found to be negatively charged, which facilitates the enhancement-mode operation. While bare Sc2O3 suffers from moisture degradation, depositing a moisture blocking layer of ALD Al2O3 can effectively eliminate this effect.

High-Performance InAlN/GaN MOSHEMTs Enabled by Atomic Layer Epitaxy MgCaO as Gate Dielectric

We have demonstrated high-performance InAlN/ GaN MOS high-electron-mobility-transistors (MOSHEMTs) with various channel lengths (L_ch) of 85-250 nm using atomic-layer-epitaxy (ALE) crystalline Mg_0.25Ca_0.75O as gate dielectric. With a nearly lattice matched epitaxial oxide, the interface between oxide and barrier is improved. The gate leakage current of MOSHEMT is reduced by six orders of magnitude compared with HEMT. An OFF-state leakage current of 3 × 10^-13 A/mm, ON/OFF ratio of 4 × 10¹², almost ideal subthreshold swing of 62 mV/decade, low drain current noise with Hooge parameter of 10^-4, and negligible current collapse and hysteresis are realized. The 85-nm Lch MOSHEMT also exhibits good ON-state performance with I_dmax = 2.25 A/mm, R_ON = 1.3 Ω · mm, and g_max = 475 mS/mm, showing that ALE MgCaO is a promising gate dielectric for GaN device applications.

Inversion-mode GaAs wave-shaped field-effect transistor on GaAs (100) substrate

Inversion-mode GaAs wave-shaped metal-oxide-semiconductor field-effect transistors (WaveFETs) are demonstrated using atomic-layer epitaxy of La2O3 as gate dielectric on (111)A nano-facets formed on a GaAs (100) substrate. The wave-shaped nano-facets, which are desirable for the device on-state and off-state performance, are realized by lithographic patterning and anisotropic wet etching with optimized geometry. A well-behaved 1 μm gate length GaAs WaveFET shows a maximum drain current of 64 mA/mm, a subthreshold swing of 135 mV/dec, and an ION/IOFF ratio of greater than 107.

Direct-Liquid-Evaporation Chemical Vapor Deposition of Nanocrystalline Cobalt Metal for Nanoscale Copper Interconnect Encapsulation

In advanced microelectronics, precise design of liner and capping layers become critical, especially when it comes to the fabrication of Cu interconnects with dimensions lower than its mean free path. Herein, we demonstrate that direct-liquid-evaporation chemical vapor deposition (DLE-CVD) of Co is a promising method to make liner and capping layers for nanoscale Cu interconnects. DLE-CVD makes pure, smooth, nanocrystalline, and highly conformal Co films with highly controllable growth characteristics. This process allows full Co encapsulation of nanoscale Cu interconnects, thus stabilizing Cu against diffusion and electromigration. Electrical measurements and high-resolution elemental imaging studies show that the DLE-CVD Co encapsulation layer can improve the reliability and thermal stability of Cu interconnects. Also, with the high conductivity of Co, the DLE-CVD Co encapsulation layer have the potential to further decrease the power consumption of nanoscale Cu interconnects, paving the way for Cu interconnects with higher efficiency in future high-end microelectronics.

Synthesis of Calcium(II) Amidinate Precursors for Atomic Layer Deposition through a Redox Reaction between Calcium and Amidines

Abstract We have prepared two new CaII amidinates, which comprise a new class of ALD precursors. The syntheses proceed by a direct reaction between Ca metal and the amidine ligands in the presence of ammonia. Bis(N,N′‐diisopropylformamidinato)calcium(II) (1) and bis(N,N′‐diisopropylacetamidinato)calcium(II) (2) adopt dimeric structures in solution and in the solid state. X‐ray crystallography revealed asymmetry in one of the bridging ligands to afford the structure [(η2‐L)Ca(μ‐η2:η2‐L)(μ‐η2:η1‐L)Ca(η2‐L)]. These amidinate complexes showed unprecedentedly high volatility as compared to the widely employed and commercially available CaII precursor, [Ca3(tmhd)6]. In CaS ALD with 1 and H2S, the ALD window was approximately two times wider and lower in temperature by about 150 °C than previously reported with [Ca3(tmhd)6] and H2S. Complexes 1 and 2, with their excellent volatility and thermal stability (up to at least 350 °C), are the first homoleptic CaII amidinates suitable for use as ALD precursors.

InGaAs 3D MOSFETs with drastically different shapes formed by anisotropic wet etching

In this work, we report on a 3D device fabrication technology achieved by applying a novel anisotropic wet etching method. By aligning channel structures along different crystal orientations, high performance 3D InGaAs devices with different channel shapes such as fins, nanowires and waves have been demonstrated. With further optimizing off-state leakage path by barrier engineering, a record high ION/IOFF over 108 and minimum IOFF~3pA/μm have been obtained from InGaAs FinFET device. Scaling metrics for InGaAs GAA MOSFETs and FinFETs are systematically studied with Lch from 800 nm down to 50 nm and WFin/WNW from 100 nm down to 20 nm which shows an excellent immunity to short channel effects.

III–V CMOS devices and circuits with high-quality atomic-layer-epitaxial La 2 O 3 /GaAs interface

By realizing a high-quality epitaxial La2O3/ GaAs(111)A interface, we demonstrate GaAs CMOS devices and integrated circuits including nMOSFETs, pMOSFETs, CMOS inverters, NAND and NOR logic gates and five-stage ring oscillators for the first time. As an exercise of III-V CMOS circuits on a common substrate with a common gate dielectric, it provides a route to realize ultimate high-mobility CMOS on Si if long-time expected breakthroughs of III-V epi-growth on Si occur.

InAs gate-all-around nanowire MOSFETs by top-down approach

InAs gate-all-around (GAA) nanowire MOSFETs are experimentally demonstrated for the first time by a top-down approach ^[1-3]. Thanks to the well-controlled nanowire release process and the novel ALD high-k/metal gate stack process, InAs nFETs with channel length (L_ch) ranging from 380 to 20 nm and nanowire width (W_NW) from 60 to 20 nm are achieved. With an EOT of 3.9 nm, high drain current of 4.3 A/mm at V_ds = V_gs = 2 V and maximum transconductance (g_max) of 1.6 S/mm at V_ds = 1 V are obtained in a device with W_NW = 20 nm and L_ch = 180 nm, normalized by the perimeter of the nanowires. A detailed scalability study (V_TH, g_m, I_ds vs. L_ch) was carried out. The devices in this study show strong dependence on the nanowire width and smaller nanowire size offers much enhanced electrical performance and better immunity from the short channel effects (SCEs).

Performance enhancement of gate-all-around InGaAs nanowire MOSFETs by raised source and drain structure

InGaAs gate-all-around (GAA) MOSFETs with implanted source and drain (S/D) structure have been demonstrated which offer large drive currents and excellent immunity to short channel effects down to deep sub-100 nm channel length [1-2]. In this work, we fabricate n⁺⁺ raised S/D InGaAs GAA MOSFETs with 10nm or 20nm thick nanowires and 200nm channel length. Maximum I_on over 1 mA/μm at V_gs-V_t=1V and V_ds=1V is obtained, which is attributed to small S/D series resistance (R_sd). The R_sd of small dimension devices is systematically studied. We find that R_sd is significantly reduced with the n⁺⁺ S/D structure compare to the implanted structure [1]. At the same time, we find that R_sd is inverse proportional to the perimeter of the nanowire on 20nm thick nanowire devices while R_sd is inverse proportional to the cross section area of the nanowire on 10nm thick nanowire devices. The significant difference confirms that the 10nm thick nanowire works in volume inversion mode while the 20nm nanowire or larger dimension still works in surface inversion mode.

DC and RF characterizations of AlGaN/GaN MOSHEMTs with deep sub-micron T-gates and atomic layer epitaxy MgCaO as gate dielectric

High performance deep sub-micron T-gate AlGaN/GaN MOSHEMTs are demonstrated using lattice matched ALE MgCaO as gate dielectric. The 120 nm-Lg MOSHEMT has an I_DMAX of 1.2 A/mm, R_on of 1.5 Ω·mm, a f_t/f_max of 101/150 GHz, with negligible hysteresis and I_G, showing the promise as a GaN MOS technology. The work at Purdue University is supported by AFOSR and the work at Harvard University is supported by ONR.