Xian Tang

A CMOS Low-Dropout Regulator With Dominant-Pole Substitution

A dominant-pole substitution (DPS) technique for low-dropout regulator (LDO) is proposed in this paper. The DPS technique involves signal-current feedforward and amplification such that an ultralow-frequency zero is generated to cancel the dominant pole of LDO, while a higher frequency pole substitutes in and becomes the new dominant pole. With DPS, the loop bandwidth of the proposed LDO can be significantly extended, while a standard value and large output capacitor for transient purpose can still be used. The resultant LDO benefits from both the fast response time due to the wide loop bandwidth and the large charge reservoir from the output capacitor to achieve the significant enhancement in the dynamic performances. Implemented with a commercial 0.18-μm CMOS technology, the proposed LDO with DPS is validated to be capable of delivering 100 mA at 1.0-V output from a 1.2-V supply, with current efficiency of 99.86%. Experimental results also show that the error voltage at the output undergoing 100 mA of load transient in 10-ns edge time is about 25 mV. Line transient responses reveal that no more than 20-mV instantaneous changes at the output when the supply voltage swings between 1.2 and 1.8 V in 100 ns. The power-supply rejection ratio at 3 MHz is -47 dB.

A charge-pump and comparator based power-efficient pipelined ADC technique

A charge-pump and comparator based technique is presented for power-efficient pipelined analog-to-digital conversion. The technique takes advantage of a passive charge pump to implement the core function of residue voltage amplification and exploits a comparator-controlled charging circuit to buffer the residue voltage to the next stage. Unlike the conventional buffer circuit using source followers, no voltage headroom is sacrificed in this voltage buffering scheme. The comparator overshoot due to comparator delay is minimized by a self-cancellation scheme. The proposed pipelined ADC technique uses only capacitors, comparators and current sources with digital calibration to achieve low power consumption. Designed and fabricated in a 0.18@mm CMOS technology, a proof-of-concept ADC has measured 39.1dB SNDR (6.2-bit ENOB) at 25MS/s while consuming 3.5mW from a 1.8V supply.

A Resistor-Based Sub-1-V CMOS Smart Temperature Sensor for VLSI Thermal Management

This paper presents a novel low-voltage CMOS smart temperature sensor targeted for VLSI thermal management. A polyresistor is used as the sensing element and digitization is performed in the time domain. The proposed temperature-sensing concept can be realized with simple circuits that operate at low supply voltages, which are compatible with the digital circuits in VLSI systems. Fabricated in 90-nm CMOS, the sensor can operate with a supply voltage as low as 0.8 V and features a supply sensitivity of 4°C/V. After 50-sample moving-average and a two-point calibration at 25°C and 45°C, the design achieves an inaccuracy of -0.6°C/0.8°C over -40°C-125°C. It dissipates only 11.8 uW at a sampling rate of 5 kS/s from a 0.9-V nominal supply.

A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s Advanced Techniques-Based Novel Intrabody Communication Receiver Analog Front End

This paper presents a low power, long-transmission distance, high data rate intrabody communication (IBC) analog receiver front end (RFE). First, to optimize the transmission performance, conventional transmission line analysis scheme is creatively adopted to the IBC design to characterize the body channel. Second, switched-capacitor filters based on sampling rate boosting technique are adopted for higher accuracy and lower power consumption. Third, a novel RFE topology is proposed to further enhance the IBC performance. The new RFE is designed and fabricated in a standard 180-nm CMOS process. Measurement results show that the RFE can successfully transmit data spanning the whole human body, around 180 cm, which is one of the longest transmission distances reported in related literatures. Furthermore, it reaches a maximum data rate of 2.5 Mb/s with a bit error rate less than 1e-7 and consumes 5.4 mW from a 1.8 V supply. The proposed RFE compares favorably to similar reported works.

A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

Novel overshoot cancellation in comparator-based pipelined ADC

In this paper, a new overshoot cancellation method is presented for comparator-based pipelined ADCs. By introducing charging and discharging operations in two adjacent stages, the large overshoot in each stage can be either tolerated as sub-ADC error or cancelled out with each other. Applying this concept, a 10-bit pipelined ADC has been designed and simulated in a 0.18-μm CMOS process. It achieves 57.2dB SNDR at 20MS/s and consumes 2.6mW under 1.8 V supply, resulting in an ENOB of 9.2-bit and an FOM of 0.221 pJ/Conv.-step.

Cascaded Network Body Channel Model for Intrabody Communication

Intrabody communication has been of great research interest in recent years. This paper proposes a novel, compact but accurate body transmission channel model based on RC distribution networks and transmission line theory. The comparison between simulation and measurement results indicates that the proposed approach accurately models the body channel characteristics. In addition, the impedance-matching networks at the transmitter output and the receiver input further maximize the power transferred to the receiver, relax the receiver complexity, and increase the transmission performance. Based on the simulation results, the power gain can be increased by up to 16 dB after matching. A binary phase-shift keying modulation scheme is also used to evaluate the bit-error-rate improvement.

A 10-bit 2 MS/s SAR ADC using reverse VCM-based switching scheme

This paper presents a successive-approximation-register (SAR) analogue-to-digital converter (ADC) using a tri-level switching scheme named as reverse VCM-based scheme which maintains good linearity without any driving and accuracy requirements on VCM. A 10-bit SAR ADC is designed in a 0.18 CMOS technology. With a unit capacitor size of 17.2 fF, the ADC consumes 41.9 μW from a 1.8 V voltage supply. The measured signal-to-noise-plus-distortion ratio (SNDR) is 59.6 dB at 2 MS/s. The figure-of-merit (FOM) is 26.9 fJ/conv.-step.

A cascode miller compensated three-stage amplifier with local Q-factor control for wide capacitive load applications

In this paper, a low power three-stage CMOS amplifiers with 375x capacitive load (Ci) drivability will be presented. By employing the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively and the physical size of the compensation capacitors is reduced. A local Q-factor control (LQC) loop is introduced to optimize the Q-factor when loading capacitance Cl changes dramatically, which is essential to improve settling performance. Also, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Implemented in standard 0.13-y«m CMOS technology, the amplifier can handle 4 pF to 1.5 nF capacitive load with at least 0.88-MHz unity-gain frequency (UGF) while consuming as low as 24.0 μW of quiescent power at 1.0-V supply voltage.

Improved Nauta transconductor for wideband intermediate-frequency gm-C filter

An improved Nauta transconductor, with output resistance for differential-mode output signals insensitive to process and tuning voltage variations, is presented in this paper. Comparing with the classical Nauta transconductor, the proposed transconductor introduces 4 auxiliary inverters only. It can increase the differential-mode output resistance, and keep the common-mode output resistance nearly no changed at the same time. The proposed transconductor has been implemented in a 7th-order transconductance-C (gm-C) band-pass filter (BPF) in a standard 0.18-μm CMOS technology. The proposed filter has achieved a bandwidth of 20 MHz under a 15-MHz center frequency. Monte Carlo simulation results show that with the same tuning voltage range, the gain deviation of the filter with proposed transconductors is reduced 4.4 dB comparing with the counterpart based on classical Nauta transconductors, and the sensitivity of the quality (Q) factor of filter poles to tuning voltage is also significantly reduced. Measurement results show that the pass-band ripple of the proposed filter is reduced 1 dB, and the stop-band attenuation is reduced 8 dB at 30 MHz.