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Dive into the research topics where Xianda Zhou is active.

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Featured researches published by Xianda Zhou.


IEEE Electron Device Letters | 2011

A Novel SONOS Gate Power MOSFET With Excellent UIS Capability

Xianda Zhou; Jacky C. W. Ng; Johnny K. O. Sin

A novel silicon-oxide-nitride-oxide-silicon gate power MOSFET is proposed and experimentally demonstrated. In the novel device, the doping concentration of the p-body is increased by an order of magnitude compared to that of the conventional power MOSFET. However, the positive shift of the threshold voltage due to the heavily doped p-body is fully compensated by the positive fixed charges preprogrammed in the silicon nitride of the oxide-nitride-oxide gate dielectric. As a result, a normal threshold voltage can be obtained, and the avalanche energy absorption of the novel device at unclamped inductive switching is 5.2 times that of the conventional power MOSFET.


IEEE Transactions on Electron Devices | 2012

UIS Analysis and Characterization of the SONOS Gate Power MOSFET

Xianda Zhou; Jacky C. W. Ng; Johnny K. O. Sin

In this paper, unclamped inductive switching (UIS) performance of the novel silicon-oxide-nitride-oxide-silicon (SONOS) gate power MOSFET (SG-MOSFET) is analyzed. The avalanche energy absorption of the SG-MOSFET at UIS is 5.2 times that of the conventional power MOSFET. Analysis shows that the improvement is due to the heavily doped p-body used in the device. Moreover, the influence of the structural parameters on the UIS performance of the device is experimentally characterized. Measurement results show that the UIS performance is not sensitive to the p+ contact width and slightly degrades with a larger gate length. Furthermore, the results show that it is promising to further improve the UIS performance of the device by using a more efficient charge trapping material in the gate dielectric to allow further increase in the p-body doping concentration.


IEEE Transactions on Electron Devices | 2013

Hot Carrier Injection Effects in the Ultrashallow Body SONOS Gate Power MOSFET

Xianda Zhou; Hao Feng; Johnny K. O. Sin

In this paper, threshold voltage (VTH) stability of the ultrashallow body silicon-oxide-nitride-oxide-silicon gate power MOSFET (SG-MOSFET) under hot carrier injection conditions is characterized and discussed. Experimental results indicate that hot electron injection will increase the VTH from 1 to 2 V in the lifetime of the device. On the other hand, hot hole injection has no significant influence on the VTH stability of the device. The different effects caused by hot electron injection and hot hole injection are explained by using numerical analysis and experimental characterization, and results suggest that the VTH stability of the ultrashallow body SG-MOSFET will be improved if the short channel effect of the structure can be suppressed.


international symposium on power semiconductor devices and ic's | 2012

Planar SONOS gate power MOSFET with an ultra-shallow body region

Xianda Zhou; Hao Feng; Johnny K. O. Sin

In this paper, a planar silicon-oxide-nitride-oxide-silicon (SONOS) gate power MOSFET (SG-MOSFET) with a 0.3 μm ultra-shallow heavily doped p-body region is presented. The ultra-shallow body provides a much reduced parasitic JFET resistance, resulting in a low specific on-resistance of 18 mΩ·mm2 for a planar device. At the same time, no punch-through problem is caused by the ultra-shallow body, and the avalanche breakdown voltage of the device is 29.5 V. The product of the on-resistance and gate charge of the ultra-shallow body SG-MOSFET is 43 mΩ·nC at VGS = 4.5 V. The non-optimized performance obtained for this structure is comparable to that of trench power MOSFETs fabricated using more advanced technologies.


IEEE Electron Device Letters | 2014

A Novel SNOS Gate-Controlled, Normally-Off p-i-n Switch

Xianda Zhou; Hao Feng; Johnny K. O. Sin

A novel silicon-nitride-oxide-silicon (SNOS) gate-controlled, normally-off p-i-n switch (SGPINS) is proposed and experimentally demonstrated. The normally-off of the SGPINS is implemented by using a fully depleted n--channel region that is controlled by an SNOS trench gate. The device has a threshold voltage of 7 V and an avalanche breakdown voltage of ~1000 V. ON-state voltage drop of the SGPINS is 1.7 V, and is ~0.6 V lower than that of an IGBT with the same non-punch-through structure, resulting in ~26% reduction in the conduction loss.


US Patent | 2011

POWER SEMICONDUCTOR FIELD EFFECT TRANSISTOR STRUCTURE WITH CHARGE TRAPPING MATERIAL IN THE GATE DIELECTRIC

Johnny K. O. Sin; Xianda Zhou


Archive | 2015

Power semiconductor devices, and methods for manufacturing same

Xianda Zhou; Johnny Kin On Sin


international symposium on power semiconductor devices and ic s | 2018

Optimization of trench sidewall for low leakage current of the sloped field plate trench edge termination

Wentao Yang; Xianda Zhou; Chao Xiao; Hao Feng; Yong Liu; Xiangming Fang; Yuichi Onozawa; Hiroyuki Tanaka; Kaname Mitsuzuka; Johnny K. O. Sin


international symposium on power semiconductor devices and ic s | 2018

Experimental characterization of the fully integrated Si-GaN cascoded FET

Jie Ren; Chak Wah Tang; Hao Feng; Huaxing Jiang; Wentao Yang; Xianda Zhou; Kei May Lau; Johnny K. O. Sin


international conference on electron devices and solid-state circuits | 2018

A One-Transistor Active Pixel Sensor Formed by A Vertical Photodiode-Gated Low-Temperature Polysilicon Thin-Film Transistor

Kai Wang; Xianda Zhou; Meng Zhang; Yitong Xu; Man Wong; Hoi Sing Kwok

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Johnny K. O. Sin

Hong Kong University of Science and Technology

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Hao Feng

Hong Kong University of Science and Technology

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Hoi Sing Kwok

Hong Kong University of Science and Technology

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Man Wong

Hong Kong University of Science and Technology

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Meng Zhang

Hong Kong University of Science and Technology

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Kai Wang

Sun Yat-sen University

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Yitong Xu

Sun Yat-sen University

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Wentao Yang

Hong Kong University of Science and Technology

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Chak Wah Tang

Hong Kong University of Science and Technology

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Huaxing Jiang

Hong Kong University of Science and Technology

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