Xiao Liyi

A Highly Reliable Memory Cell Design Combined With Layout-Level Approach to Tolerant Single-Event Upsets

In this paper, a highly reliable radiation hardened by design memory cell (RHD12) using 12 transistors in a 65-nm CMOS commercial technology is proposed. Combining with layout-level design, the TCAD mixed-mode simulation results indicate that the RHD12 not only can fully tolerant the single-event upset occurring on any one of its single nodes but can also tolerant single-event multiple-node upsets in a single memory cell, which are caused by charge sharing. Moreover, a set of HSPICE post-simulations are done to evaluate the RHD12 and other state-of-the-art memory cells, which show that our proposed memory cell has better performance, considering the area, power consumption, and access time.

A new synchronization algorithm for VHDL-AMS simulation

VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. A mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorithm is adopted in the simulator. Using the new algorithm the analog kernel does not need to synchronize the digital kernel at each digital event time point. The efficiency of the new synchronization algorithm is tested by examples. Simulation results show the newly developed algorithm can speed up the simulation.VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. h mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorithm is adopted in the simulator. Using the new algorithm the analog kernel does not need to synchronize the digital kernel at each digital event time point. The efficiency of the new synchronization algorithm is tested by examples. Simulation results show the newly developed algorithm can speed up the simulation.

Analysis of process variations impact on the single-event transient quenching in 65 nm CMOS combinational circuits

Single-event transient pulse quenching (Quenching effect) is employed to effectively mitigate WSET (SET pulse width). It enhanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, parameter variation is another serious issue that significantly affects circuit’s performance and single-event response. Monte Carlo simulations combined with TCAD (Technology Computer-Aided Design) simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. Studies show that charge sharing induce a wider WSET spread range. The difference of WSET range between no quenching and quenching is smaller in NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) simulation than that in PMOS’ (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor), so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. The individual parameter analysis indicates that gate oxide thickness (TOXE) and channel length variation (XL) mostly affect SET response of combinational circuits. They bring 14.58% and 19.73% average WSET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases.

A novel oscillation-based BIST for ADCs

An oscillation based BIST scheme for ADCs was proposed. A novel technique was used to timing output codes of ADCs by digital mode. In the BIST structure, the test signal was controlled by the feedback circuit to oscillate between two transition edges of ADCs. The rising and falling time of the test signal during oscillation period was in direct proportion to the code width of ADCs under testing. By timing the rising or falling time and comparing it with an ideal time, the offset error, differential non-linearity (DNL), integral non-linearity (INL) and gain error can be achieved.

Test control of TAM-bus: a solution for testing SoC

The SoC (system-on-chip) based on reusable embedded IP (Intellectual Property) introduces new challenges for the test, since the SoC integrator may not know the implementation of the IP cores that are usually embedded in chip deeply. IEEE P1500 standard for embedded core test (SECT) is a standard-under-development that aims at improving ease of testing SoC. The SECT standardizes the core wrapper and the core test language (CTL), and leaves the design of test access mechanism (TAM) to the SoC integrator. The TAM-bus we proposed is a P1500 compliant TAM. This paper describes the control of TAM-bus. With a novel interface to the chip level JTAG test access port (TAP), the TAM control module can provide the control of the TAM and wrappers. The final test architecture is flexible and configurable. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The hardware overhead increases only 0.17% due to the TAM-bus and the TAM controller. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.The SoC (system-on-chip) based on reusable embedded IP (Intellectual Property) introduces new challenges for the test, since the SoC integrator may not know the implementation of the IP cores that are usually embedded in chip deeply. IEEE P1500 standard for embedded core test (SECT) is a standard-under-development that aims at improving ease of testing SoC. The SECT standardizes the core wrapper and the core test language (CTL), and leaves the design of test access mechanism (TAM) to the SoC integrator. The TAM-bus we proposed is a P1500 compliant TAM. This paper describes the control of TAM-bus. With a novel interface to the chip level JTAG test access port (TAP), the TAM control module can provide the control of the TAM and wrappers. The final test architecture is flexible and configurable. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The hardware overhead increases only 0.17% due to the TAM-bus and the TAM controller. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.

TCAD simulation of single event effects induced by pulsed laser

In this paper, the laser radiation model is built up with TCAD (Technology Computer Aided Design) tool. And a PN junction is chosen for simulating the Single Event Effects (SEEs) induced by the pulsed laser as well as heavy ions. The transient current responses related with SEEs are simulated, and also the distributions of the electrostatic potential and carrier generation inside the device are plotted. Simulation results demonstrate that the pulsed laser can simulate single event effects effectively in spite of the different mechanisms responsible for generating electron-hole pairs between pulsed laser and heavy ions. And it is indicated that the pulsed laser simulation with TCAD is significant for the laser experiments.

Research on laser radiation for simulating dose rate effects in semiconductor materials

In this paper, a laser radiation model based on TCAD is built up. With this model, some simulations of laser irradiating semiconductor material are presented. And also simulations of gamma ray irradiating semiconductor material are given. By comparing the simulation results the relationship between laser intensity and gamma dose rate is obtained. The results demonstrate that the laser radiation model is practicable in TCAD for reliability analysis and the laser simulation technique is reliable to simulate dose rate effect.

Novel technique for P-hit single-event transient mitigation using enhance dummy transistor

As technology down scales, single event transient (SET) is more vulnerable than before in combinational circuits. This paper proposes a novel layout technique to mitigate the SET effect in combinational circuits. Based on 65nm CMOS process, technology computer aided design (TCAD) SET simulations are conducted on conventional layout, source-isolation layout, dummy transistor layout and the proposed layout. Heavy ions with different liner energy transfer (LET) values, inject angles and striking locations are simulated. The results indicate that, the proposed layout have considerable effect on decreasing the SET pulse width than other layouts. Compare with dummy transistor the proposed enhance dummy transistor have no additional area cost.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity (ELDRS) under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

Mixed-signal behavioral modeling for QPSK digital communication system

In this paper, a behavioral model of the QPSK digital communication system is presented using VHDL-AMS. The whole system can be divided into several parts. So, on the basis that the behavioral models of the parts are established first, the behavioral model of the system can be accomplished with the top structural description. Then the models can be verified by simulation.