Ye Yizheng

Optimal Schemes for ADC BIST Based on Histogram

Two testing time reducing schemes of histogram-based BIST (built-in self test) for testing of ADC IPs (intellectual property) are presented in this paper. The first technique uses parallel time decomposition to minimize not only chip area overhead but also testing time in the ADC BIST based on histogram. The second scheme named fold linear histogram-based BIST is proposed to further reduce testing time during computation of DNL (differential nonlinearity) and INL (integral nonlinearity) with little hardware overhead increase. Pseudo-algorithms are given to derive DNL, INL, offset and gain error. A practical implementation is described and the performance is evaluated

An efficient ASIC implementation of SHA-1 engine for TPM

With the development of trusted computing systems, TCG promotes TPM as the core hardware building block. The SHA-1 engine in TPM contributes the performance of the whole platform. In this paper, the data flow latencies of the SHA-1 hardware implementation are analyzed, and the bottlenecks are optimized by special arithmetic structures. As a result, the frequency of the optimized structure has increased by 43%. And the performance of this SHA-1 engine is also compared with other SHA-1 engines by frequency, area and throughput.

The improvement for transaction level verification functional coverage

For hardware design, simulation is still the primary approach for functional verification of circuit descriptions written in hardware design language. The coverage metrics measure the process of validation and indicate the unexplored parts of the design. The paper describes a coverage-directed method that is suitable for transaction level verification. The approach is based on random test generation, and the coverage is increased by using a fault insertion method. Using case studies, we show how to establish the testbed and how this approach has been used to improve the quality of transaction level functional verification.

Implementation of RSA cryptoprocessor based on Montgomery algorithm

The RSA algorithm is a major method in implementing a public key cryptosystem. On the basis that the Montgomery algorithm can modular-multiply in a fast way, this paper presents a hardware implementation of a 1024-bit RSA cryptoprocessor. It has been shown that the processor can encrypt 1024 bit message in less than 0.65 seconds, with which a 3 mm/sup 2/ die area. It is suitable for smart IC cards.

Design and implementation of high-speed Reed-Solomon decoder

This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon decoder based on the modified Euclidean algorithm. A new multiplier and inversion for GF(2/sup m/) are implemented on the composite field GF(2/sup 2n/) (m=2n), which offers lower hardware requirements compared to standard Mastrovito multiplier and ROM respectively. By setting the new initial conditions of MEA, not only decoding latency but also hardware overheads of RS (204,188) decoder is reduced greatly compared to the conventional architecture with the same decoding rate. The complexity of the proposed RS decoder is about 118,000 gates, and the decoding latency is only 220 clock cycles and has a throughput of 800 Mbit/s using 0.25 /spl mu/m CMOS process.

A low-cost BIST scheme for ADC testing

A low-cost BIST scheme based on linear histogram for testing ADC is presented in this paper. A parallel time decomposition technique is presented to minimize not only hardware overhead but also testing time of the BIST scheme based on histogram. An area-efficient linear triangular waveform generator is discussed as test stimulus. The technique uses digital delta-sigma noise shaping to generate the on-chip precise analog stimulus and simplify the analog circuit of the generator at same time. A practical implementation is described and the performance is evaluated

A new synchronization algorithm for VHDL-AMS simulation

VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. A mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorithm is adopted in the simulator. Using the new algorithm the analog kernel does not need to synchronize the digital kernel at each digital event time point. The efficiency of the new synchronization algorithm is tested by examples. Simulation results show the newly developed algorithm can speed up the simulation.VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. h mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorithm is adopted in the simulator. Using the new algorithm the analog kernel does not need to synchronize the digital kernel at each digital event time point. The efficiency of the new synchronization algorithm is tested by examples. Simulation results show the newly developed algorithm can speed up the simulation.

Designing AHB/PCI bridge

The PCI Local Bus is a high performance, 32-bit or 64-bit bus with multiplexed address and data lines. It is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards and processor/memory systems. The AHB of AMBA (Advanced Microcontroller Bus Architecture) is also designed for high-performance, high clock frequency system modules. In SoC design, the AHB acts as a high-performance system backbone bus. The function of AHB/PCI bridges is to map various control signals and address spaces from one bus into those of another. This paper presents the design of the AHB/PCI bridge.

Design procedure for optimizing CMOS low noise operational amplifiers

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier. The design procedure focuses on the noise performance, which is the key requirement for low noise operational amplifiers. Based on the noise level and other specifications such as bandwidth, signal swing, slew rate, and power consumption, the device sizes and the biasing conditions are derived. In order to verify the proposed design procedure, a three-stage operational amplifier has been designed. The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.

2.5Gb/s CMOS RGC transimpedance amplifier

A novel low noise CMOS regulated cascode (RGC) transimpedance amplifier, which can be used in the front-end of 2.5 Gbit/s optical communication system, is presented. Active inductor peaking technique, active feedback and source follower are used to improve the -3 dB bandwidth. Simulation results using 0.18 mum standard CMOS process show the transimpedance gain is 71.51 dBOmega, the -3 dB bandwidth is 2.2 GHz, and the average noise current spectral density is 8.3 pA/radicHz. When the input current is 35 muA, the output eye-diagram voltage amplitude is 92 mV, and the eye-diagram is clean. The power consumption is 10 mW.