Xiao Shimao

A novel 2.95?3.65 GHz CMOS LC-VCO using tuning curve compensation

This paper presents a new CMOS LC-VCO with a 2.95–3.65 GHz tuning range. The large tuning range is achieved by tuning curve compensation using a novel varactor configuration, which is mainly composed of four accumulation-mode MOS varactors (A-MOS) and two bias voltages. The proposed varactor has the advantages of optimizing quality factor and tuning range simultaneously, linearizing the effective capacitance and thus greatly reducing the amplitude-to-phase modulation (AM-PM) conversion. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Measured phase noise is lower than –91 dBc at 100 kHz offset from a 3.15 GHz carrier while measured tuning range is 21.5% as the control voltage varies from 0 to 1.8 V. The VCO including buffers consumes 2.8 mA current from a 1.8 V supply.

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

A constant loop bandwidth fractional-N frequency synthesizer for portable civilian global navigation satellite system (GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work- ing regions, the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized band- width is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an in-band phase noise lower than -93 dBc at a 10 kHz offset and a spur less than -70 dBc; the bandwidth varies by 3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area (without the LO tested buffer) is 0.5 mm 2 .

A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Close-loop phase noise measured is lower than −95 dBc at 200 kHz offset while the measured tuning range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2.

A low-phase-noise LC-VCO with an enhanced-Q varactor for use in a high-sensitivity GNSS receiver

An LC-VCO with an enhanced quality factor (Q/ varactor for use in a high-sensitivity GNSS receiver is presented. An enhanced A-MOS varactor is composed of two accumulation-mode MOS (A-MOS) varactors and two bias voltages, which show the improved Q and linearization capacitance-voltage (C -V / curve. The VCO gain (KVCO/ is compensated by a digital switched varactors array (DSVA) over entire sub-bands. Based on the characteristics of an A-MOS, the varactor in a DSVA is a high Q fixed capacitor as it is switched off, and a moderate Q tuning varactor when it is switched on, which keeps the maximal Q for the LC-tank. The proposed circuit is fabricated in a 0.18 m 1P6M CMOS process. The measured phase noise is better than -122 dBc/Hz at a 1 MHz offset while the measured tuning range is 58.2% and the variation of KVCO is close to 21% over the whole of the sub-bands and the effective range of the control voltage. The proposed VCO dissipates less than 5.4 mW over the whole operating range from a 1.8 V supply.

A low-power CMOS frequency synthesizer for GPS receivers

A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 m CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscil- lator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of -87 dBc/Hz at 15 kHz offset, with spurs less than -65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm 2 .