Xiao-Yong Liu

Design of U-Shape Channel Tunnel FETs With SiGe Source Regions

In this brief, a novel U-shape-channel tunneling field-effect transistor (UTFET) with a SiGe source region is investigated by 2-D technology computer aided design simulation. The enlarged tunneling area and enhanced tunneling rate dramatically increase the tunneling current when the device is turned on. Meanwhile, the off-leakage current of UTFET is suppressed because of the extended physical channel length. The on-state tunneling current of UTFET can be further improved by introducing an n+-doped Si delta layer under the source region. The inserted delta layer significantly shortens the band-to-band tunneling path, enlarges tunneling area, and thus enhances the tunneling rate of this device. The average value of the subthreshold swing (SS) of the optimized UTFET is 58 mV/dec when VGS is varied from 0 to 0.46 V. Using the SiGe-source UTFET structure with a delta layer, the merits of low leakage current, high drive current, and ultralow SS can be realized simultaneously.

A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation

Faster at the Gate Advanced designs will be needed to continue to improve the performance of the main components of high-speed computing, metal-oxide semiconductor field-effect transistors (MOSFETs) and floating-gate (FG) MOSFETs. Wang et al. (p. 640) fabricated a semi-floating gate (SFG) transistor in which a tunneling field-effect transistor couples the positively doped floating gate to the negatively doped drain region. The charge stored on the SFG was used to shift the voltage threshold for switching the transistor, which in turn sped up its operation and lowered the power consumed. These devices were used for ultrahigh-speed memory and in light sensing and imaging. An embedded tunneling field-effect transistor speeds switching by varying the voltage threshold of the main gate electrode. As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra–high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.

Low-Temperature Ohmic Contact Formation in GaN High Electron Mobility Transistors Using Microwave Annealing

In this letter, a low-temperature microwave annealing (MWA) method is first reported for the formation of ohmic contact to AlGaN/GaN high electron mobility transistors (HEMTs). Compared with the traditional GaN devices annealed by rapid thermal annealing (RTA), MWA-HEMTs can achieve a low ohmic contact resistance with much smoother surface of ohmic contacts. The spike mechanism is observed in our ohmic contact annealed by microwave under a low-temperature condition. Besides, MWA-HEMTs have higher ION/IOFF ratio and lower gate leakage current than the fabricated RTA-HEMTs in this letter.

Impacts of Thermal Atomic Layer-Deposited AlN Passivation Layer on GaN-on-Si High Electron Mobility Transistors

Thermal atomic layer deposition (ALD)-grown AlN passivation layer is applied on AlGaN/GaN-on-Si HEMT, and the impacts on drive current and leakage current are investigated. The thermal ALD-grown 30-nm amorphous AlN results in a suppressed off-state leakage; however, its drive current is unchanged. It was also observed by nano-beam diffraction method that thermal ALD-amorphous AlN layer barely enhanced the polarization. On the other hand, the plasma-enhanced chemical vapor deposition (PECVD)-deposited SiN layer enhanced the polarization and resulted in an improved drive current. The capacitance-voltage (C-V) measurement also indicates that thermal ALD passivation results in a better interface quality compared with the SiN passivation.

AlGaN/GaN MISHEMTs with AlN gate dielectric grown by thermal ALD technique

Recently, AlN plasma-enhanced atomic layer deposition (ALD) passivation technique had been proposed and investigated for suppressing the dynamic on-resistance degradation behavior of high-electron-mobility transistors (HEMTs). In this paper, a novel gate dielectric and passivation technique for GaN-on-Si AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) is presented. This technique features the AlN thin film grown by thermal ALD at 400°C without plasma enhancement. A 10.6-nm AlN thin film was grown upon the surface of the HEMT serving as the gate dielectric under the gate electrode and as the passivation layer in the access region at the same time. The MISHEMTs with thermal ALD AlN exhibit enhanced on/off ratio, reduced channel sheet resistance, reduction of gate leakage by three orders of magnitude at a bias of 4 V, reduced threshold voltage hysteresis of 60 mV, and suppressed current collapse degradation.

Characterization and Optimization of a Single-Transistor Active Pixel Image Sensor with Floating Junction Connected to Floating Gate

The application of semifloating gate transistor (SFGT) as the single-transistor active pixel image sensor (APS) is investigated in this paper. This single-transistor (1T) APS can realize the functions of the conventional 3T CMOS image sensor. The device operation mechanism, optimization methods, and transient behavior measurements will be discussed. Because the floating junction of this device is connected to the floating gate, special behaviors such as floating gate voltage pinning effects were observed. The transient time measurement emulating the exposure procedure also confirmed the light sensing function as a single-transistor image sensor.

Investigation of Temperature Dependence, Device Scalability, and Modeling of Semifloating-Gate Transistor Memory Cell

A semifloating-gate transistor had been proposed and its memory function has been demonstrated recently. In this paper, we further investigate its temperature dependency, device scalability, and device modeling. The high-temperature behavior is studied by measuring its endurance, retention, and disturbance immunity at 85 °C. The device scalability down to the 14-nm technology node is investigated by simulation. Its macrodevice model for circuit design is also developed. Finally, a memory array with the specific peripheral circuits is designed using the device model developed in this paper.

Investigation of a GaN-on-Si HEMT optimized for the 5th-generation wireless communication

In this paper, AlGaN/GaN heterostructure high electron mobility transistors (HEMTs) have been fabricated on GaN-on-Si substrate. These devices were studied for the application of the 5^th generation (5G) wireless communication. The geometric parameters such as gate length (L_g), cap length (L_cap) and gate-to-source distance (L_gs) are optimized so that the cut-off frequency reaches 38.8 GHz. It is found that decreasing L_g and L_gs can both improve drain current and peak transconductance (G_mmax). Highest drain current of 1 A/mm at V_g=2V and biggest G_mmax of 240 mS/mm was achieved. A fabricated device with L_g of 100 nm, L_cap of 300 nm and L_gs of 800 nm showed a f_T of 38.8 GHz and a f_MAX of 60 GHz at V_ds=5V which can meet the requirement of the 5G application.

Investigation of spin-on-dopant for fabricating high on-current tunneling field effect transistor

Spin-on-dopant and rapid thermal diffusion are used as the doping method for fabricating planar tunneling field effect transistor (TFET) in this paper to acquire abrupt doping profile and high surface doping concentration. Due to the heavy surface doping the on-current of TFET is enhanced. The ambipolar characteristics of TFET are also inhibited by reducing the drain doping concentration.

Impact of geometric dimensions on the behavior of GaN MIS-HEMT fabricated on patterned sapphire substrate

In this paper, an AlGaN/GaN based MIS-HEMT using Al2O3 dielectric as gate insulator was fabricated. We adopted the patterned sapphire as the substrate (PSS) of high-quality AlGaN GaN epitaxial layers. We also studied the influence of different gate-drain space (L_gd) on breakdown voltage (V_BD) and on-state resistance (R_on) of GaN HEMT fabricated on patterned sapphire substrate. A breakdown voltage of 105 V was obtained with the L_gd of 2 μm and gate width of 32 μm. The specific on resistance was 4.7 Ω·mm when L_gd equals 0.5 μm. Meanwhile, it is found that the devices fabricated on the wet-etched pyramidal patterned sapphire substrate GaN exhibit better drive current stability than that of the devices on the conventional GaN-on-Sapphire substrate.