Xiaobao Yu

A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration

A fully integrated dual-channel reconfigurable GNSS receiver supporting Compass/GPS/GLONASS/Galileo systems is implemented in 65 nm CMOS. The receiver incorporates two independent channels to receive dual-frequency signals simultaneously. GNSS signals located at the 1.2 GHz or 1.6 GHz bands are supported, with their bandwidths programmable among 2.2 MHz, 4.2 MHz, 8 MHz, 10 MHz, and 18 MHz. By implementing a flexible frequency plan with a low/zero-IF architecture and reconfigurable analog baseband circuits, only one frequency synthesizer is required to provide the local oscillator (LO) frequency for two channels, thereby avoiding any LO crosstalk. Analog baseband circuits employ operational amplifiers that are capable of power scaling, in order to minimize power consumption across different operating modes. An I/Q mismatch calibration module placed prior to the complex-IF bandpass filter is implemented to improve the image rejection ratio. The receiver achieves a minimum 1.88 dB noise figure, an average 50 dB image rejection ratio, and a 64 dB dynamic range with 1 dB steps of gain-adjustment, with a total power consumption of 31-44 mW. Finally, experimental verification combining both the receiver and a digital baseband shows a positioning result comparable to commercial chips.

An Efficiency-Enhanced Stacked 2.4-GHz CMOS Power Amplifier With Mode Switching Scheme for WLAN Applications

A stacked 2.4-GHz CMOS power amplifier (PA) with a mode switching scheme is proposed to enhance the back-off efficiency for wireless local area network applications. By means of dynamically tuning the bias and optimal load with a power-detecting controller, the proposed mode switching scheme effectively improves the power-added efficiency (PAE) of the PA by ×2 at 5-dB back-off power. Besides, with the transistor stacking and envelope-tracked self-biasing techniques, the PA, powered by a 5.6-V supply, achieves an output P1dB of 27 dBm with a PAE of 26.1% and an output P1dB of 22 dBm with a PAE of 21.8% in high-power mode and low-power mode, respectively, while occupying only a 1.5- mm2 die area in 180-nm CMOS. In the closed-loop power-detecting mode, the PA achieves an adjacent channel leakage ratio of -22.6 dBc and an error vector magnitude of -26.9 dB at 23-dBm output power for 120-Mb/s 7.6-dB peak-to-average power-ratio 64 quadrature amplitude modulation 802.11n signals.

Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver

A power-scalable reconfigurable filter with in-phase/quadrature (I/Q) imbalance calibration for a multimode Global Navigation Satellite Systems (GNSS) receiver is presented. The filter is reconfigurable as either a fifth-order complex bandpass filter exhibiting a tunable intermediate frequency (4.092, 6.138, 10.23, 12.296, 13.29, 18.4, and 20.442 MHz) and bandwidth (2.2, 4.2, 8, 10, and 18 MHz) or a third-order low-pass filter with tunable bandwidth (5 and 9 MHz). A flexible current-reuse operational amplifier with a power-scaling technique is proposed to lower the power consumption, and the image-rejection ratio is improved by almost 20 dB by introducing an I/Q imbalance calibration circuit before the filter. The filter, which was implemented in 65-nm CMOS, consumes 2.9-19.5 mW in different modes, with the I/Q calibration circuit consuming 0.9 mW.

A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS

A fully-integrated dual-channel reconfigurable GNSS receiver supporting GPS/Compass/Galileo/GLONASS in 65nm CMOS is presented. The receiver has two independent channels to support simultaneous dual-frequency reception, and can be reconfigured to receive various GNSS signals located in 1.2GHz or 1.57GHz band, which have different signal bandwidth including 2.2MHz, 4.2MHz, 8MHz, 10MHz and 18MHz. By flexible frequency plan, low-IF/zero-IF architecture switching and flexible analog baseband circuits, only one frequency synthesizer is adopted to provide local oscillation (LO) for two channels simultaneously, which could avoid the LO crosstalk issue. Analog baseband circuits employ operational amplifiers capable of power scaling to optimize power consumption among various mode operations. Besides, an I/Q mismatch calibration module placed ahead of the IF complex bandpass filter is implemented to improve image rejection ratio. The receiver finally achieves 2.2dB noise figure, an average of 50dB image rejection ratio, and 64dB dynamic range with 1dB gain-adjusting steps, while consuming a minimum of 31mW power.

A Fully Integrated 60-GHz 5-Gb/s QPSK Transceiver With T/R Switch in 65-nm CMOS

A fully integrated 60-GHz 5-Gb/s quadrature phase-shift keying (QPSK) transceiver with the transmit/receive (T/R) switch in 65-nm CMOS is presented. By utilizing the co-design of the T/R switch with the power amplifier (PA)/low-noise amplifier, π-type wideband passive network technique, as well as the modified distributed-amplifier-based PA, the RF bandwidth of the transmitter (TX)/receiver (RX) is extended to 5 GHz. An inductorless wideband programmable gain amplifier with negative capacitive neutralization, consisting of two modified Cherry-Hooper amplifier stages, provides 18-dB variable gain range with enough bandwidth. Due to the proposed bandwidth extension techniques, the measured double-side link bandwidth of the TX/RX is wider than 5 GHz so that 5-Gb/s QPSK communication could be supported. A direct QPSK modulator and mixed-signal QPSK demodulator are integrated to avoid the high-power high-complexity analog-digital converter/digital-analog converter and high-speed digital baseband processing. Together with the integrated T/R switch, the power consumption and the cost of the transceiver are significantly lowered while achieving up to 5-Gb/s data rate. The local oscillating signals and various clocks are provided by a fully differential phase-locked loop frequency synthesizer with -97.2-dBc/Hz phase noise at 1-MHz offset from a 40-GHz carrier. The measured error vector magnitude of the TX is -21.9 dB, while the bit error rate of the RX with a -52-dBm sine-wave input is below 8e-7 when transmitting/receiving 5-Gb/s data. The transceiver is powered by 1.0- and 1.2-V supply (except the phase-frequency detector and charge-pump in the frequency synthesizer, which are powered by a 2.5-V supply) and consumes 135 mW in the TX mode and 176 mW in the RX mode, with a chip area of 3 mm × 2 mm.

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PAs operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by ×3.24 and ×1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by ×2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.

A Sub-GHz low-power transceiver with PAPR-tolerant power amplifier for 802.11ah applications

A fully-integrated Sub-GHz low-power transceiver (TRX) for 802.11ah applications is presented. The receiver takes both advantages of Low-IF/Zero-IF architectures while supporting 1/2/8MHz reconfigurable signal bandwidth. A Σ-Δ fractional-N PLL with Class-C VCO is employed to provide the LOs. In order to enhance the power amplifier (PA) back-off efficiency, a Peak-to-Average-Power-Ratio (PAPR) tolerant technique is proposed with the aid of a power control loop to dynamically detect the input signal PAPR and flexibly reconfigures the PAs operation modes. With digitally-assisted self-calibrations for LO leakage and image rejection, the transmitter obtains -51.6dBc LO leakage and 51.2dBc image rejection ratio (IRR). A JESD207 interface is also included to communicate with the digital baseband. Implemented in 180nm CMOS, the receiver achieves 4dB NF and dissipates 18.9mW from a 1.7V supply. The CMOS PA achieves 13.6dBm output P1dB with 25.5% PAE in high power mode (HPM) and ×2.61 PAE improvement at 7dB back-off power in low power mode (LPM).

A PAPR-Aware Dual-Mode Subgigahertz CMOS Power Amplifier for Short-Range Wireless Communication

A peak-to-average power ratio (PAPR)-aware dual-mode power amplifier (PA) for short-range wireless communication in the subgigahertz band is proposed in this brief. By carefully choosing the bias, the dual-mode PA achieves the measured output P1 dB (OP1 dB) of 13.6 dBm with a PAE of 25.5%. Furthermore, a dynamic load modulation network is utilized to optimize the PAs efficiency at back-off power. A power-control loop is proposed to detect the input signal PAPR in real time and flexibly reconfigure the PAs operation modes. With these proposed techniques, the PAE has been improved by ×2.61 at 7-dB back-off power. The measurement shows that the subgigahertz-band PA archives an adjacent channel leakage ratio (ACLR1) of -37.3 dBc and an average/peak error vector magnitude of -30.4 dB/-20.5 dB at 8.9-dBm output power for ~5-dB-PAPR 16-quadrature-magnitude-modulation LTE signals with 5-MHz bandwidth with the power control loop enabled. The PAPR-aware dual-mode PA, powered by a 2-V supply, occupies a 2.52-mm2 die area in a 180-nm CMOS.

A 49-dB DR wide locking range hybrid AGC for an ISM-band receiver in 0.18 um CMOS

A wide locking range hybrid automatic gain control (AGC) loop for an ISM-band receiver is presented. It is composed of a three-stage Programmable Gain Amplifier (PGA), a differential-output Received Signal Strength Indicator (RSSI), a SAR ADC and control algorithm logic. The indicators transfer function is realized in three segments, each of them covering 20dBm input range, in order to achieve higher sensitivity. The PGA gain can be configured either automatically by the AGC loop, or manually through the SPI interface. Implemented in 0.18um CMOS, measurement results show that the PGA dynamic range covers from 0.2 to 49.3dB, with 0.98 dB gain steps on average. The RSSI achieves maximum 70mV/dBm input sensitivity and 0.3-1.4V output range with a simulated maximum settling time of 8us. The proposed AGC consumes 3.2 mA current from a 1.7V supply.

An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS

An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS is presented. Direct QPSK modulation is implemented during the first up-conversion, followed by the final up-conversion mixer and power amplifier (PA) as well as on-chip T/R switch. Distributed amplifier technique is utilized to extend the bandwidth of PA. Along with other bandwidth extension techniques, in-band gain variation in signal link is minimized to improve the error vector magnitude (EVM). To reject common-mode noise and improve phase noise performance, a 40GHz fully-differential PLL frequency synthesizer is implemented to provide LO signals and various clocks. The measured output power is 6.4dBm at 60GHz, with 1.2dB gain variation over >6GHz bandwidth. On-chip 27-1 PRBS generators are used to measure the transmitter performance, and the measured EVM is -21.9dB with 5Gb/s QPSK modulation. The transmitter and the PLL & LO distribution network consume 73mW and 62mW, respectively.