Yun Yin

An Efficiency-Enhanced Stacked 2.4-GHz CMOS Power Amplifier With Mode Switching Scheme for WLAN Applications

A stacked 2.4-GHz CMOS power amplifier (PA) with a mode switching scheme is proposed to enhance the back-off efficiency for wireless local area network applications. By means of dynamically tuning the bias and optimal load with a power-detecting controller, the proposed mode switching scheme effectively improves the power-added efficiency (PAE) of the PA by ×2 at 5-dB back-off power. Besides, with the transistor stacking and envelope-tracked self-biasing techniques, the PA, powered by a 5.6-V supply, achieves an output P1dB of 27 dBm with a PAE of 26.1% and an output P1dB of 22 dBm with a PAE of 21.8% in high-power mode and low-power mode, respectively, while occupying only a 1.5- mm2 die area in 180-nm CMOS. In the closed-loop power-detecting mode, the PA achieves an adjacent channel leakage ratio of -22.6 dBc and an error vector magnitude of -26.9 dB at 23-dBm output power for 120-Mb/s 7.6-dB peak-to-average power-ratio 64 quadrature amplitude modulation 802.11n signals.

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PAs operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by ×3.24 and ×1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by ×2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.

A Sub-GHz low-power transceiver with PAPR-tolerant power amplifier for 802.11ah applications

A fully-integrated Sub-GHz low-power transceiver (TRX) for 802.11ah applications is presented. The receiver takes both advantages of Low-IF/Zero-IF architectures while supporting 1/2/8MHz reconfigurable signal bandwidth. A Σ-Δ fractional-N PLL with Class-C VCO is employed to provide the LOs. In order to enhance the power amplifier (PA) back-off efficiency, a Peak-to-Average-Power-Ratio (PAPR) tolerant technique is proposed with the aid of a power control loop to dynamically detect the input signal PAPR and flexibly reconfigures the PAs operation modes. With digitally-assisted self-calibrations for LO leakage and image rejection, the transmitter obtains -51.6dBc LO leakage and 51.2dBc image rejection ratio (IRR). A JESD207 interface is also included to communicate with the digital baseband. Implemented in 180nm CMOS, the receiver achieves 4dB NF and dissipates 18.9mW from a 1.7V supply. The CMOS PA achieves 13.6dBm output P1dB with 25.5% PAE in high power mode (HPM) and ×2.61 PAE improvement at 7dB back-off power in low power mode (LPM).

A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1–1.5-GHz Multistandard Applications

A reconfigurable dual-mode power amplifier (PA) with an integrated transmit/receive (T/R) switch in 65-nm CMOS is presented. The PA can be reconfigured into linear mode or switching mode. In the linear mode, it achieves >19 dBm OP1 dB with >20% PAE over 0.1-1.5 GHz; in the switching mode, the maximum saturation output power of 23.2 dBm with the peak PAE of 60% is obtained. By utilizing the asymmetrical topology and stacked techniques, the T/R switch demonstrates ~0.5-dB TX insertion loss, >27-dB TX-RX isolation, and 24.8 dBm IP1 dB across 0.1-1.5 GHz. This brief proposes, for the first time, a CMOS dual-mode PA with an integrated T/R switch for multistandard applications.

A 0.1–5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications

A 0.1-5.0 GHz 65 nm CMOS reconfigurable transmitter for private network wireless communications is presented. The transmitter integrates a 0.1-1.5 GHz high-efficiency dual-mode power amplifier to support low-cost narrowband applications and a 0.45-5.0 GHz efficiency-optimized pre-power amplifier to support high-performance wideband applications. A wideband PLL frequency synthesizer, DACs with reconfigurable sampling rate and the reconfigurable digital baseband processing with standard JESD207 interface are all included to implement the highly-integrated transmitter. Specifically, with the proposed digitally-assisted self-calibration technique for LO leakage and image rejection, the transmitter achieves 52 dBc LO leakage and >53 dBc image rejection ratio (IRR), showing 20 dB and 30 dB improvement compared with the un-calibrated cases, respectively. The system verifications have demonstrated an EVM of 1.7% for 905 MHz EDGE with 19.5 dBm output power, and an EVM of 3.2% for LTE Band42 with 5.5 dBm output power. This proposed transmitter has achieved the comparable or even better performance in linearity, noise floor and power consumption compared with the state-of-the-art reconfigurable transmitters.

A 180nm CMOS wireless transceiver by utilizing guard band for narrowband IoT applications

A fully-integrated wireless transceiver (TRX) is presented for 750~960MHz narrowband IoT applications by utilizing the guard band of mobile communication systems. The TRX consists of a low-IF receiver with 180 kHz signal bandwidth, a mixed-signal polar transmitter with 3.75 kHz signal bandwidth and a fractional-N frequency synthesizer. Current passive mixer is employed in the low-IF receiver to achieve lower 1/f noise and higher linearity. The on-chip I/Q imbalance calibration is integrated to improve the image rejection ratio (IRR) which could be realized automatically cooperated with one FPGA. The transmitter features polar architecture and inverse class-D PA to achieve high output power and efficiency. The thermometer coding and binary-coding-based array placement simplify the DPA layout and reduce the mismatch between the DPA cells. The RX achieves 4.01dB NF, 48dB IRR and 5~65dB dynamic range. The DPA provides 23.2dBm maximum saturation power with 44.5% PAE. Furthermore, TX system verifications demonstrate 3.87% EVM for 891MHz n/4-DQPSK signals at 18.87dBm output power with -40dBc out-of-band rejection. The transmitter achieves a dynamic range from -35dBm to 20dBm while the demodulation threshold of the system is 10% (EVM).

A fully-integrated reconfigurable transceiver for narrowband wireless communication in 180nm CMOS

A fully integrated reconfigurable transceiver (TRX) in 180nm CMOS for 750-960MHz narrowband applications is presented. The low-cost TRX consists of a low-IF receiver with 180 kHz signal bandwidth, a digital polar transmitter with 3.75 kHz signal bandwidth and a fractional-N frequency synthesizer. The receiver features a passive current mode mixer to improve the linearity and avoid the noise degradation due to the 1/f noise. The on-chip I/Q mismatch calibration is introduced to improve the image rejection ratio (IRR). The Inverse Class-D power amplifier (PA) is integrated into the transmitter to achieve high output power and efficiency, and the pre-distortion is exploited to realize the DPA linearization. Besides, the digital transmitter performs the power output by digitally controlling the DPA unit array. In order to compensate for PVT variations, the DCOC, I/Q mismatch, AFC and filter frequency tuning are all integrated in the transceiver. The RX achieves 5.1dB NF, 48dB IRR and 60dB gain dynamic range with 1dB step. The DPA provides the maximum 24.2dBm output power with 28.9% PAE. Furthermore, the TX demonstrates 4.9% EVM for 891MHz DQPSK signals at 19.09dBm output power.

A 0.1–5GHz SDR transmitter with dual-mode power amplifier and digital-assisted I/Q imbalance calibration in 65nm CMOS

A 0.1-5GHz Software-Defined Radio (SDR) transmitter in 65nm CMOS is presented. The transmitter integrates a dual-mode power amplifier (PA) for 0.1-1.5GHz low-cost narrowband applications (such as Industry Specific Applications, 2G, ZigBee), while a three-sub-band pre-power amplifier (PPA) is used for 0.45-5GHz high performance wideband applications (3G, 4G and etc.). A digital-assisted I/Q imbalance calibration circuit is proposed ahead the TX chain to pre-compensate I/Q mismatch in IF and LO modules. Analog baseband utilizes power scalable technique to optimize power consumption among different modes. The transmitter achieves -63.9dBc image rejection ratio (IRR) and -56.9dBc LO leakage rejection. In narrowband modes, the dual-mode PA provides >19dBm output P1dB with >20% PAE in its linear mode, and 23.2dBm maximum saturation power with 60% peak PAE in the switching mode. In wideband modes, the PPA provides maximum 9dBm output P1dB. F urthermore, system verifications demonstrate 0.5% EVM for 905MHz GSM at 19.5dBm output power. And the transmitter achieves -42.6dBc ACLR and 1.4% EVM for 2.3GHz LTE20 at 6.2dBm output.

A 0.1∼4GHz receiver and 0.1∼6GHz transmitter with reconfigurable 10∼100MHz signal bandwidth in 65nm CMOS

A 8.12mm2 0.1-4GHz receiver and 0.1~6GHz transmitter with reconfigurable 10~100MHz signal bandwidth in 65nm CMOS is presented. Rx features two single-ended LNAs in parallel, passive current down-conversion with 25% duty-cycle LOs, 5th/7th-order reconfigurable baseband filtering and IIP2/frequency tuning/IQ calibration. It achieves NF of 3~8dB over 0.1-4GHz and 21mA current consumption for 2.3GHz LTE with 20MHz signal bandwidth. Fully-integrated Tx features reconfigurable PPAs with transformer differential-single-ended conversion output, a low-noise sub-path and high dynamic range main-path as well as LO leakage and image rejection calibration. It achieves 1.7% EVM for 1.8GHz WCDMA with 1.5dBm output power, -31/-51 ACLR1/ACLR2 for 2.3GHz LTE with 20MHz bandwidth at 3dBm output power, <;-42dBc LO feedthrough and >;51dBc image rejection.

A 0.1–5.0GHz self-calibrated SDR transmitter with −62.6dBc CIM3 in 65nm CMOS

A 0.1-5.0GHz self-calibrated SDR transmitter is presented. A complete self-calibration scheme is proposed to alleviate non-ideal effects, including RF operation frequency deviation, output power control, LO leakage and image rejection. A power mixer front-end and a V-I converter with 3rd-order nonlinearity cancellation are introduced to achieve -62.6dBc CIM3 at 5.3dBm output power in LTE band42. A Class-AB/F dual-mode PA is integrated for narrowband applications. With the self-calibration, the transmitter has obtained good robustness in RF operation frequency self-tuning, LO leakage and image rejection performance over 0.1-5.0GHz, and achieved 24.5dBm Pout with 0.7% EVM, 20dBm Pout with 1.6% EVM, 6.2dBm Pout with 2.1% EVM for GSM/EDGE/LTE signals, respectively.