Baoyong Chi

Low-Power Transceiver Analog Front-End Circuits for Bidirectional High Data Rate Wireless Telemetry in Medical Endoscopy Applications

State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-mum CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 mum CMOS.

A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO

This paper presents a low-power transceiver with a reconfigurable sliding-IF (intermediate frequency) architecture targeted for wireless body area networks hubs covering 400 MHz and 2.4 GHz bands. By using this architecture, a 1608-1988 MHz PLL synthesizer with only 21% tuning range can fully cover all the available bands around 400 MHz and 2.4 GHz as defined by IEEE 802.15.6 NB (narrow band) and ZigBee. The dual-band transceiver has been designed in 0.18 μm CMOS process. The design consists of a receiver with a wideband front-end and a reconfigurable amplifier-mixer, a transmitter with a reconfigurable two stage full quadrature mixer, a ΣΔ fractional-N PLL and some auxiliary circuits. The measurement result has demonstrated that the proposed transceiver can satisfy the dual-band requirements with comparable or even better performance in noise, receiver sensitivity and power consumption compared to previously-reported transceivers for only a single band.

A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration

A fully integrated dual-channel reconfigurable GNSS receiver supporting Compass/GPS/GLONASS/Galileo systems is implemented in 65 nm CMOS. The receiver incorporates two independent channels to receive dual-frequency signals simultaneously. GNSS signals located at the 1.2 GHz or 1.6 GHz bands are supported, with their bandwidths programmable among 2.2 MHz, 4.2 MHz, 8 MHz, 10 MHz, and 18 MHz. By implementing a flexible frequency plan with a low/zero-IF architecture and reconfigurable analog baseband circuits, only one frequency synthesizer is required to provide the local oscillator (LO) frequency for two channels, thereby avoiding any LO crosstalk. Analog baseband circuits employ operational amplifiers that are capable of power scaling, in order to minimize power consumption across different operating modes. An I/Q mismatch calibration module placed prior to the complex-IF bandpass filter is implemented to improve the image rejection ratio. The receiver achieves a minimum 1.88 dB noise figure, an average 50 dB image rejection ratio, and a 64 dB dynamic range with 1 dB steps of gain-adjustment, with a total power consumption of 31-44 mW. Finally, experimental verification combining both the receiver and a digital baseband shows a positioning result comparable to commercial chips.

A Low-Power High-Data-Rate ASK IF Receiver With a Digital-Control AGC Loop

A low-power high-data-rate ASK IF receiver is proposed. It consists of one digital-control automatic-gain-control (AGC) loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of the programmable-gain amplifier (PGA) in the AGC loop is discretely adjusted by a gain-control block to eliminate the multidigit analog-to-digital converter. Due to the high sensitivity of the ASK detector, a large controllable input range can be obtained in the AGC loop. The ASK IF receiver has been implemented in 0.18-μm CMOS, and the overall current consumption is 1.21 mA with a supply voltage of 1.8 V. The ASK receiver achieves a 2-Mb/s data rate with an IF carrier frequency of 10 MHz, and an input signal amplitude ranges from 180 μV to 900 mV.

An Efficiency-Enhanced Stacked 2.4-GHz CMOS Power Amplifier With Mode Switching Scheme for WLAN Applications

A stacked 2.4-GHz CMOS power amplifier (PA) with a mode switching scheme is proposed to enhance the back-off efficiency for wireless local area network applications. By means of dynamically tuning the bias and optimal load with a power-detecting controller, the proposed mode switching scheme effectively improves the power-added efficiency (PAE) of the PA by ×2 at 5-dB back-off power. Besides, with the transistor stacking and envelope-tracked self-biasing techniques, the PA, powered by a 5.6-V supply, achieves an output P1dB of 27 dBm with a PAE of 26.1% and an output P1dB of 22 dBm with a PAE of 21.8% in high-power mode and low-power mode, respectively, while occupying only a 1.5- mm2 die area in 180-nm CMOS. In the closed-loop power-detecting mode, the PA achieves an adjacent channel leakage ratio of -22.6 dBc and an error vector magnitude of -26.9 dB at 23-dBm output power for 120-Mb/s 7.6-dB peak-to-average power-ratio 64 quadrature amplitude modulation 802.11n signals.

A self-healing 2.4GHz LNA with on-chip S 11 /S 21 measurement/calibration for in-situ PVT compensation

This paper presents a 2.4GHz, reconfigurable RF LNA using on-chip peak detection and calibration to measure and optimize its input impedance (S11) and gain (S21) in-situ, compensating for the unpredictable effects of process, voltage and temperature (PVT) variations. Measurement results show that the calibration of the LNA across PVT corners improves the S11 by 5.1dB, S21 by 3dB, while not significantly degrading the Noise Figure (0.22dB degradation) and linearity (1.7dBm degradation).

A 47.6–71.0-GHz 65-nm CMOS VCO Based on Magnetically Coupled

A wide tuning range millimeter-wave voltage-controlled oscillator (VCO) based on a magnetically coupled π-type LC network in 65-nm CMOS is proposed. By configuring the switched negative-resistance unit, the VCO can oscillate at the even mode or the odd mode of the magnetically coupled π-type LC network, thus the tuning range is widened without introducing the switch loss into the resonator. The proposed VCO achieves a measured continuous tuning range of 39%, from 47.6 to 71.0 GHz. The measured phase noise for a 47.6-GHz carrier at the even mode and 56.2-GHz carrier at the odd mode are -110.3 and -107.3 dBc/Hz at 10-MHz offset with a corresponding FOMT of -185.5 and -183.9 dBc/Hz, respectively. The measured phase noise in the whole frequency tuning range varies from -101.7 to -113.4 dBc/Hz at 10-MHz offset, while the corresponding figure-of-merit (FOM) and FOMT vary from -167.8 to -179.0 dB and -179.6 to 190.6 dB, respectively. The VCO core consumes 8.9-10.4-mA current from 1.0-V power supply and 320 × 230 μm 2 die area.

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A 60-GHz dual-mode power amplifier (PA) with efficiency enhancement at low output power in 65-nm bulk CMOS is presented. The PA consists of two cascaded common-source driver stages and one transformer-based output stage. The dual-mode output stage is reconfigured into a stacked-transistor amplifier with a 2.5-V power supply in high-power (HP) mode for high-power-handling capability and a cascode amplifier with a 1.2-V power supply in low-power (LP) mode for efficiency enhancement at low output power. The measured results show that the presented PA achieves a small-signal gain of 23.5/21.3 dB, a saturated output power value of 17.6/11.4 dBm, a 1-dB output power value of 12.5/4.7 dBm, and a peak power-added-efficiency (PAE) value of 20.4%/13.3% in the HP/LP mode at 60 GHz, respectively. The PAE at 10-dBm output power is improved by 2.8x (10.6% versus 3.8%) by utilizing the LP mode compared with the HP-mode-only PA. The total chip area is 0.68 mm × 0.35 mm, including pads.

-Type LC Network

A power-scalable reconfigurable filter with in-phase/quadrature (I/Q) imbalance calibration for a multimode Global Navigation Satellite Systems (GNSS) receiver is presented. The filter is reconfigurable as either a fifth-order complex bandpass filter exhibiting a tunable intermediate frequency (4.092, 6.138, 10.23, 12.296, 13.29, 18.4, and 20.442 MHz) and bandwidth (2.2, 4.2, 8, 10, and 18 MHz) or a third-order low-pass filter with tunable bandwidth (5 and 9 MHz). A flexible current-reuse operational amplifier with a power-scaling technique is proposed to lower the power consumption, and the image-rejection ratio is improved by almost 20 dB by introducing an I/Q imbalance calibration circuit before the filter. The filter, which was implemented in 65-nm CMOS, consumes 2.9-19.5 mW in different modes, with the I/Q calibration circuit consuming 0.9 mW.

A 60-GHz CMOS Dual-Mode Power Amplifier With Efficiency Enhancement at Low Output Power

A miniaturized Marchand balun combiner is proposed for a W-band power amplifier (PA). The proposed combiner reduces the electrical length of the transmission lines (transmission line) from about 80 ^° to 30 ^°, when compared with a conventional Marchand balun combiner. Implemented in a 1-V 65-nm CMOS process, the presented PA achieves a measured saturated output power of 11.9 dBm and a peak power-added efficiency of 9.0% at 87 GHz. The total chip area (with pads) is 0.77×0.48 mm², where the size of the balun combiner is only 0.36×0.13 mm².