Xiaofang Zhou

A novel hybrid Matched Filter structure for IEEE 802.22 standard

Spectrum sensing is the key for Cognitive Radio (CR) systems such as IEEE 802.22 standard in improving the Quality of Service (QoS) of secondary user while avoiding harmful interference to primary user (PU) of the allocated spectrum. In this paper, we reviewed the traditional MFs (Matched Filter) properties and proposed a novel hybrid MF structure which is designed to perform spectrum sensing function in IEEE 802.22 standard. This structure mixes segmented MF with parallel MFs, and overcomes MFs bottleneck — frequency offset without sacrificing its advantage. We revealed some properties of this novel structure and demonstrate a case in 802.22 standard and compare it with other papers. The result shows that our novel structure has advantages over other spectrum sensing methods.

Generic Mixed-Radix FFT Pruning

Compared with traditional Fast Fourier Transform (FFT) algorithms, FFT pruning is more computationally efficient in those cases where some of the input values are zero and/or some of the output components are not needed. In this letter, a novel pruning scheme is developed for mixed-radix and high-radix FFT pruning. The proposed approach is applicable over a wide range of FFT lengths and input/output pruning patterns. In addition, it can effectively employ the benefits of high-radix FFT algorithms that have lower computational complexity.

A wide band differentially switch-tuned CMOS monolithic quadrature VCO with a low Kvco and high linearity

A wide band, differentially switch-tuned CMOS monolithic LC-VCO is presented in this paper, as well as a frequency divider for high linearity, low Kvco quadrature signal generation. A linearity control logic is proposed. The Kvco linearity is improved to be lower than 17.68MHz/V. By using the proposed CML DFF, the operating frequency of the frequency divider is increased by 20% with a power consumption of 3.6mW. The proposed design has been fabricated and verified in a 0.18@mm CMOS process. The QVCO is tuned in a combined way of continuous technology and 4bit binary switch capacitor array (SCA) discrete tuning technology. The measurement indicates that the QVCO has a 19.7% tuning range from 1.816 to 2.213GHz. The measured phase noise is -112.25dBc/Hz at 1MHz offset from the 1.819GHz carrier and draws a current of 4.0mA around at a 1.8V supply.

A smart platform with cognitive techniques for narrowband power line communication

Power Line Communication (PLC) is becoming a strong alternative technology which enables communication on the ubiquitous electrical power supply networks. To overcome the main problem of PLC-the harsh channel characteristics, we combine the idea of Cognitive Radio (CR) and a smart SoC platform for narrowband PLC baseband processing is presented. In our platform, spectrum energy detection is made to cognize the channel condition, and accordingly the transmission parameters like the carrier frequency, modulation scheme, error codes and data rate could be adapted dynamically with good configurability to obtain best performance. Results have shown that CR scheme works efficiently and high throughput is achieved on our platform.

A constant-gain time-amplifier with digital self-calibration

This paper presents a closed-loop time-amplifier (TA) with a novel self-calibration technique by adjusting the output capacitance of the conventional TA. The gain of the TA is stabilized, with an input of 0.05∼1 Td (one buffer delay), over a large Process-Voltage-Temperature (PVT) variation: from SS to FF process corner, +/−10% supply voltage, and −40 to 80 °C. The proposed TA is designed with SMIC 0.18-µm mixed-signal CMOS process. Simulation results show that the gain deviation of TA is well controlled within 0.35% under all circumstances, with regard to the gain in typical PVT condition, and the whole circuit consumes 600 µA with an input signal of 40 MHz1.

A New Bandgap Reference for High-Resolution Data Converters

In this paper, a CMOS bandgap reference (BGR) for high-resolution data-converters is proposed and analyzed. The proposed BGR circuit is derived and modified from a recently developed low-voltage BGR. It combines two different branches of conventional BGR into one PMOS transistor, avoiding the matching requirement of the current mirror. The low temperature-susceptible current is used to generate high and low references for data-converters. This modified architecture is verified by a 0.35-um CMOS BGR circuit. In the demo design, the 2.7 V and 0.6 V voltage and 12 uA current references for a sigma-delta analog-to-digital modulator all obtain a temperature coefficient (TC) of about 20 ppm/K. With a tiny adjustment, the proposed BGR also has the potential to work at low supply-voltage.

Network-on-Chip for Turbo Decoders

The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High Speed Downlink Packet Access (HSDPA) are analyzed. Based on this analysis, two techniques, subnetworking and calculation sequence, are proposed for reducing the complexity of the NoC. The implementation results show that the proposed structure gives an improvement of 53% for HSDPA and 133% for LTE in throughput/area efficiency compared with state-of-the-art NoC solutions.

Reconfigurable baseband processing platform for communication systems

New trends in wireless communication systems require multi-standard coexistence and high data rates. In order to meet these requirements, we propose a reconfigurable baseband platform with coarse grained heterogeneous execution units and flexible interconnections, which are controlled by configuration information. In addition, we demonstrate the effectiveness of our approach in three sample implementations, namely RFID, WLAN OFDM and MIMO-OFDM systems. The performance results reveal that this platform is flexible enough to handle various baseband operations with good efficiency and at reasonable resource cost.

Reconfigurable baseband processing architecture for communication

The development of multiple communication standards and services has created the need for a flexible and efficient computational platform for baseband signal processing. Using a set of heterogeneous reconfigurable execution units (RCEUS) and a homogeneous control mechanism, the proposed reconfigurable architecture achieves a large computational capability while still providing a high degree of flexibility. Software tools and a library of commonly used algorithms are also proposed in this paper to provide a convenient framework for hardware generation and algorithm mapping. In this way, the architecture can be specified in a high-level language and it also provides increased hardware resource usage. Finally, we evaluate the systems performance on representative algorithms, specifically a 32-tap finite impulse response (FIR) filter and a 256-point fast Fourier transform (FFT), and compare them with commercial digital signal processor (DSP) chips as well as with other reconfigurable and multi-core architectures.

Software Defined Radio architecture using a multicasting Network-on-Chip

Software Defined Radio (SDR) allows dynamically changing protocols and functions in order to provide flexible, multiple-standard services to users. A reconfigurable baseband architecture having a set of coarse-grained, heterogeneous execution units is one strategy which can meet this requirement. However, while we can integrate a large number of execution units onto a chip, conventional bus structures may not be able to support the amount of traffic between the functional units due to the shared nature of the bus. In this paper, an SDR baseband platform is mapped onto two different types of on-chip networks, a multicasting CDMA-based network and a conventional 2D-mesh network. Synthesis is performed for both cases using a 0.13 micron CMOS technology library and comparative results for performance and area are provided.