Wenqing Lu

Reconfigurable baseband processing platform for communication systems

New trends in wireless communication systems require multi-standard coexistence and high data rates. In order to meet these requirements, we propose a reconfigurable baseband platform with coarse grained heterogeneous execution units and flexible interconnections, which are controlled by configuration information. In addition, we demonstrate the effectiveness of our approach in three sample implementations, namely RFID, WLAN OFDM and MIMO-OFDM systems. The performance results reveal that this platform is flexible enough to handle various baseband operations with good efficiency and at reasonable resource cost.

Reconfigurable baseband processing architecture for communication

The development of multiple communication standards and services has created the need for a flexible and efficient computational platform for baseband signal processing. Using a set of heterogeneous reconfigurable execution units (RCEUS) and a homogeneous control mechanism, the proposed reconfigurable architecture achieves a large computational capability while still providing a high degree of flexibility. Software tools and a library of commonly used algorithms are also proposed in this paper to provide a convenient framework for hardware generation and algorithm mapping. In this way, the architecture can be specified in a high-level language and it also provides increased hardware resource usage. Finally, we evaluate the systems performance on representative algorithms, specifically a 32-tap finite impulse response (FIR) filter and a 256-point fast Fourier transform (FFT), and compare them with commercial digital signal processor (DSP) chips as well as with other reconfigurable and multi-core architectures.

A heterogeneous reconfigurable baseband architecture for wireless LAN transceivers

An efficient and configurable computational platform is indispensable in order to meet multiple wireless communications standards. We have developed a heterogeneous reconfigurable architecture to support the arithmetic, logic and signal processing functions which are required for transceivers used in standardized wireless local area networks. Each execution unit in this reconfigurable architecture focuses on a certain general operation, so that the combination of them can complete the various algorithms. We demonstrate the effectiveness of our approach through an implementation of the baseband of IEEE 802.11a/b/g standards and evaluate its performance.

An Efficient Multi-protocol RFID Interrogator Baseband Processor based on a Reconfigurable Architecture

With the continued development of RFID technology, a large number of RFID tags are being deployed having different protocols. Hence, a multiprotocol interrogator which can support all of these alternatives has become a design requirement for many systems. While multifunction capability may be implemented using a high performance DSP, CPU or FPGA, those solutions have a large area cost, so an innovative architecture is needed. Starting from an analysis of the algorithms in RFID systems, we propose a reconfigurable architecture for baseband processing to realize the various protocols in the ISO18000 standard. The structure has been specifically designed to support all of the functions needed, so that it performs very efficiently with low area cost. This design has been post-layout simulated with a clock frequency of up to 83 MHz, and the core area is 4 mm2 in a UMC 0.18 mum CMOS process. Compared with other existing processors, the proposed architecture is much more efficient for this application area.

A 0.18um 3.3mW double-balanced CMOS active mixer

This paper introduces a Gilbert-type active CMOS mixer integrated in 0.18 um process. Radio frequency signals are feed to the input ports of mixer, and then down-converted to IF band of 1 MHz. No inductor is employed in this circuit to reduce the circuit size. The circuit requires a 1.8 V voltage source and consumes only 3.3 mW when in normal mode. With gain increasing strategy, simulation results indicate the active mixer has a conversion gain of 6.2 dB, IIP3 of -4.4 dBm, noise figure of 12.8 dB.It is suitable for low-power frequency translation applications.

A CMOS polyphase low-IF filter with on-chip frequency control

A CMOS polyphase low-IF filter with on-chip frequency control for a 2.4 GHz wireless LAN is presented. Designed in a 1.8 V, 0.18 mum standard CMOS process, this Chebyshev polyphase filter has a 7th order 0.5 dB passband ripple. An on-chip auto frequency control module is designed for the variation of process in order to get the required sensitivity of the filter. This filter consumes 1.74 mW including the on-chip control module and the total chip area is 0.276 mm2.

A 2.4-GHz spur-cancelled fractional-n frequency synthesizer with PFD/DAC structure for WSN application

A 2.4-GHz wideband fractional-N frequency synthesizer utilizing PFD/DAC structure for Wireless Sensor Network (WSN) Application is presented. In this synthesizer, hybrid of phase/frequency detector and compensated digital-to-analog converter (PFD/DAC) is utilized to achieve phase noise performance as an integer-N synthesizer. The synthesizer is implemented with wide 400 kHz loop bandwidth and 4 us setting time. The chip occupies 1.9 mm2 and consumes 16.4 mA at 1.8-V supply.

FFT design for OFDM-based cognitive radio using a reconfigurable baseband processing architecture

Cognitive Radio (CR) has been proposed to address the apparent paradox between spectrum scarcity and spectrum underutilization. It requires the use of a reconfigurable architecture to support a wide range of operating modes. In the case of OFDM-based CR, several subcarriers could interfere with licensed (i.e., the primary) users, so there may be a large number of zero-valued input/output points of the IFFT/FFT and the standard FFT algorithms are not efficient in such a situation. In this paper, we discuss how a more appropriate FFT algorithm, transform decomposition, can be mapped onto a reconfigurable baseband processing architecture. Two mapping methods are proposed to meet various user requirements.

A 2.4GHz highly linear class C power amplifier in 0.18 μ m CMOS technology

This paper presents a class C power amplifier (PA) with high efficiency and linearity , implemented in 0.18 mum CMOS technology. The third harmonic is controlled by Biasing while the second harmonic is limited by employing the differential structure. It delivers a power gain of 19.7 dB at the input power of -12 dBm with power added efficiency (PAE) of 43%. The second and third harmonics are -35.1 dBc and -36.0 dBc. In order to drive a single-ended load, an off-chip balanced-unbalanced (balun) circuit is also designed and analyzed in this paper.