Xiaojun Weng

Top-Gated Epitaxial Graphene FETs on Si-Face SiC Wafers With a Peak Transconductance of 600 mS/mm

In this letter, we present state-of-the-art performance of top-gated graphene n-FETs and p-FETs fabricated with epitaxial graphene layers grown on Si-face 6H-SiC substrates on 50-mm wafers. The current-voltage characteristics of these devices show excellent saturation with on-state current densities (I_on) of 0.59 A/mm at V_ds = 1 V and 1.65 A/mm at V_ds = 3 V. I_on/I_off ratios of 12 and 19 were measured at V_ds = 1 and 0.5 V, respectively. A peak extrinsic g_m as high as 600 mS/mm was measured at V_ds = 3.05 V, with a gate length of 2.94 ¿m. The field-effect mobility versus effective electric field (E_eff) was measured for the first time in epitaxial graphene FETs, where record field-effect mobilities of 6000 cm²/V·s for electrons and 3200 cm²/V·s for holes were obtained at E_eff ~ 0.27 MV/cm .

Correlating Raman Spectral Signatures with Carrier Mobility in Epitaxial Graphene: A Guide to Achieving High Mobility on the Wafer Scale

We report a direct correlation between carrier mobility and Raman topography of epitaxial graphene (EG) grown on silicon carbide (SiC). We show the Hall mobility of material on SiC(0001) is highly dependent on thickness and monolayer strain uniformity. Additionally, we achieve high mobility epitaxial graphene (18100 cm(2)/(V s) at room temperature) on SiC(0001) and show that carrier mobility depends strongly on the graphene layer stacking.

Nucleation of epitaxial graphene on SiC(0001).

A promising route for the synthesis of large-area graphene, suitable for standard device fabrication techniques, is the sublimation of silicon from silicon carbide at elevated temperatures (>1200 degrees C). Previous reports suggest that graphene nucleates along the (110n) plane, known as terrace step edges, on the silicon carbide surface. However, to date, a fundamental understanding of the nucleation of graphene on silicon carbide is lacking. We provide the first direct evidence that nucleation of epitaxial graphene on silicon carbide occurs along the (110n) plane and show that the nucleated graphene quality improves as the synthesis temperature is increased. Additionally, we find that graphene on the (110n) plane can be significantly thicker than its (0001) counterpart and appears not to have a thickness limit. Finally, we find that graphene along the (110n) plane can contain a high density of structural defects, often the result of the underlying substrate, which will undoubtedly degrade the electronic properties of the material. Addressing the presence of non-uniform graphene that may contain structural defects at terrace step edges will be key to the development of a large-scale graphene technology derived from silicon carbide.

Epitaxial graphene materials integration: effects of dielectric overlayers on structural and electronic properties.

We present the integration of epitaxial graphene with thin film dielectric materials for the purpose of graphene transistor development. The impact on epitaxial graphene structural and electronic properties following deposition of Al(2)O(3), HfO(2), TiO(2), and Ta(2)O(5) varies based on the choice of dielectric and deposition parameters. Each dielectric film requires the use of a nucleation layer to ensure uniform, continuous coverage on the graphene surface. Graphene quality degrades most severely following deposition of Ta(2)O(5), while the deposition if TiO(2) appears to improve the graphene carrier mobility. Finally, we discuss the potential of dielectric stack engineering for improved transistor performance.

Fabrication and Electrical Properties of Si Nanowires Synthesized by Al Catalyzed Vapor−Liquid−Solid Growth

The synthesis of epitaxially oriented Si nanowires at high growth rates (>1 microm/min) was demonstrated on (111) Si substrates using Al as the catalyst. The use of high H(2) and SiH(4) partial pressures was found to be effective at reducing problems associated with Al oxidation and nanowire nucleation, enabling growth of high aspect ratio structures at temperatures ranging from 500 to 600 degrees C with minimal tapering of the diameter. Because of the high growth rate observed, the Al catalyst is believed to be in the liquid state during the growth. Four-point resistance measurements and back-gated current-voltage measurements indicate that the wires are p-type with an average resistivity of 0.01 +/- 0.004 Omega-cm. These results suggest that Al is incorporated into the Si nanowires under these conditions at concentrations higher than the solubility limit (5-6 x 10(18) cm(-3)) for Al in Si at 550 degrees C. This work demonstrates that Al can serve as both an effective catalyst and p-type dopant for the growth of Si nanowires.

Coexistence of tunneling magnetoresistance and electroresistance at room temperature in La0.7Sr0.3MnO3/(Ba, Sr)TiO3/La0.7Sr0.3MnO3 multiferroic tunnel junctions

Tunnel junctions composed of two ferromagnetic electrodes separated by a ferroelectric barrier were fabricated from epitaxial La0.7Sr0.3MnO3/Ba0.95Sr0.05TiO3/La0.7Sr0.3MnO3 trilayers. Typical R−H curves with sharp-switched resistance states (magnetic parallel and antiparallel) of magnetic tunnel junctions have been observed up to room temperature. After applying a poling voltage, which reverses the barrier polarization, both the parallel and antiparallel resistance states will switch to different values. Clear tunneling magnetoresistance and tunneling electroresistance, hence the four resistance states have been observed at room temperature.

Correlation of growth stress and structural evolution during metalorganic chemical vapor deposition of GaN on (111) Si

Compositionally graded AlGaN buffer layers enable the growth of thicker crack free layers of GaN on (111) Si than is possible with an AlN buffer layer. Using cross sectional transmission electron microscopy and in situ stress measurements, it is shown that a compressive growth stress is incorporated in the GaN layer when the graded AlGaN buffer layer is thick enough to accommodate all microstructural evolution, which is primarily a reduction in threading dislocation density with thickness during growth. Most of the dislocation density reduction is observed to occur when the film is growing under a compressive stress. This compressive stress arises from the changing lattice parameter due to grading and helps to offset the tensile stress generated by microstructural evolution. It also helps to decrease the tensile thermal expansion mismatch stress during cooling and thus reduces film cracking.

Effect of AlN interlayers on growth stress in GaN layers deposited on (111) Si

Thin (∼10nm) AlN interlayers have previously been used to mitigate stress and cracking in GaN epitaxial layers grown on Si substrates. However, multiple AlN interlayers are typically required for the growth of thick (>1μm) GaN as the initial compressive mismatch stress introduced by the AlN interlayer transitions to a tensile stress within 0.5μm. To better understand the reasons for the transition, in situ monitoring and transmission electron microscopy have been used to study stress and structural evolution in undoped GaN layers deposited on high temperature (1050–1100°C) AlN interlayers by metal-organic chemical-vapor deposition. The results show that transition of the initial compressive stress to a final tensile stress is associated with a reduction in the density of dislocations introduced either by the pseudosubstrate or the interlayer itself.

The nature of catalyst particles and growth mechanisms of GaN nanowires grown by Ni-assisted metal?organic chemical vapor deposition

The structure and chemistry of the catalyst particles that terminate GaN nanowires grown by Ni-assisted metal-organic chemical vapor deposition were investigated using a combination of electron diffraction, high-resolution transmission electron microscopy, and x-ray energy dispersive spectrometry. The crystal symmetry, lattice parameter, and chemical composition obtained reveal that the catalyst particles are Ni(3)Ga with an ordered L 1(2) structure. The results suggest that the catalyst is a solid particle during growth and therefore favor a vapor-solid-solid mechanism for the growth of GaN nanowires under these conditions.

Top-Gated Graphene Field-Effect Transistors Using Graphene on Si (111) Wafers

In this letter, we report the first experimental demonstration of wafer-scale ambipolar field-effect transistor (FET) on Si (111) substrates by synthesizing a graphene layer on top of 3C-SiC(111)/Si(111) substrates. With lateral scaling of the source-drain distance to 1 μm in a top-gated layout, the ON-state current of 225 μA/μm and peak transconductance of > 40 μS/μm were obtained at Vds = 2 V, which is the highest performance of graphene-on-Si FETs. The peak field-effect mobilities of 285 cm2 /Vs for holes and 175 cm2 /Vs for electrons were demonstrated, which is higher than that of ultra-thin-body SOI (n, p) MOSFETs.