Xiaowu Zhang

Package-level Si-based micro-jet impingement cooling solution with multiple drainage micro-trenches

High heat flux removal is a major consideration in the design of a number of microelectronic devices. A Si micro cooler, combining the merits of both micro-channels and jet impingement, has been developed to dissipate the heat flux for the IC chip. Multiple drainage micro-trenches (MDMT) have been designed inside the cooler to avoid the negative cross-flow effect between the nearby nozzles. The effect of the micro-trench width on the required pressure drop is analyzed. Three types of nozzle/trench arrangements are studied. Several simulations are conducted to study the thermal effect of the distance between nozzle and trench, when the same pumping power is supplied. Without cross-flow effect, full developed jet impingement can be achieved for each nozzle. With 0.2W pumping power, the spatially average heat transfer coefficient is around 15×104W/m2K. To dissipate 350W/cm2 heat flux uniformly loaded on the Si chip, the designed micro cooler can maintain the maximum chip temperature rise lower than 25°C, and low temperature variation within the chip. The designed cooler with MDMT is also quite effective for cooling the chip with concentrated heat fluxes.

GaN-on-Si hotspot thermal management using direct-die-attached microchannel heat sink

GaN-on-Si device posts new challenge to thermal management with its highly concentrated heat flux dissipation from HEMT. In order to characterize GaN-on-Si hotspot and to develop an effective cooling solution, a customized thermal test chip is built with highly doped resistors to produce tiny (150 × 350 μm2) hotspots. Direct-die-attached copper microchannel heat sink is used instead of the conventional slap on heat sink to significantly improve the heat removal rate from the device. By using Infra-red (IR) thermography, the current experimental work demonstrated the cooling capability of microchannel heat sink up to 11.9 kW/cm2 hotspot heat flux with a maximum hotspot temperature of 175 °C.

The 1 st Level & 2 nd Level Solder Joint Reliability Co-design for Larger Die Flip Chip Package

This work focuses on co-design of the 1st level and 2nd level solder joint reliability analysis of a flip chip package, with large die. Model with all the layered structures for the build up substrate is compared with the compact model of equivalent substrate. Two 1st level solder bumps are modeled along with the 2nd level solder balls. The fatigue life of 2nd level solder joint is estimated by the Darveauxs method. Inelastic strain energy density per cycle accumulated in the solder bumps during thermal cycling is used to predict the trend of fatigue life for the 1st level bumps. Model with and without heat spreader are considered in this study. Then a series of parametric study is performed by varying different crucial package dimensions which play an important role in solder fatigue life. Effects of die thickness, substrate thickness and heat spreader type on solder fatigue life are analyzed in this paper.

Effects of detailed substrate modeling and solder layout design on the 1 st and 2 nd level solder joint reliability for the large die FCBGA

This paper discusses the thermo-mechanical design and analysis of a large die FCBGA. This work focuses on co-design of the 1st level and 2nd level solder joint reliability analysis of a flip chip package emphasizing the effect of details substrate modeling and solder layout design. Model with all the layered structures for the build up substrate is compared with the compact model of equivalent substrate. The fatigue life of the 2nd level solder joint is estimated by the Darveauxs method. Inelastic strain energy density per cycle accumulated in the solder bumps during thermal cycling is used to predict the trend of fatigue life for the 1st level bumps. Effects of die thickness, substrate thickness and heat spreader on solder fatigue life are analyzed. As the maximum inelastic strain energy density occurs at the solder ball near the die edge, different solder ball layouts are studied by changing the distance of the critical solder ball from die edge. In addition, to further improve the packaging design of large die FCBGA, the fatigue life of most critical solder ball is investigated by means of the design of experiment (DOE). The final results could be used as a design guideline to improve the fatigue life of both the 1st and 2nd level solder joints of the package.

Heat dissipation improvement with diamond heat spreader on hybrid Si micro-cooler for GaN devices

A diamond heat spreader of small size has been directly attached between the chip and the hybrid Si micro-cooler for thermal performance improvement of the GaN-on-Si device. In the fabricated test vehicle, one hotspot of size 450×300μm2 is used to mimic the heating area of one GaN unit. The microwave CVD diamond of high thermal conductivity was bonded through TCB process. With the diamond heat spreader attached on the reduced by 25.7% and 26.1%, respectively. Two types of diamond heat spreader of different thermal conductivities are tested and compared. High improvement of heat dissipation capability has been demonstrated.

Development of a jet-based Si micro-cooler with multiple drainage micro-trenches

Micro-fluid cooling solution is one of the most effective techniques for thermal management of high heat fluxes. A jet-based Si micro-cooler with multiple drainage micro-trenches has been developed for micro-electronic thermal management. An inlet/outlet flow arrangement layer has been introduced to achieve uniform pressure distribution for each nozzle. The effect of three types of arrangement structures on the hydraulic and thermal performance of the micro-cooer have been analyzed and compared using the fluid-solid coupling simulation models. The nozzle length effect and nozzle shape effect on the pressure variation inside cooler and the cooling capability have been studied. The test vehicle with the new nozzle/trench layer is fabricated using double-side DRIE process. The assembly of the stacked micro-cooler and the Si thermal test chip is finished using the two-steps optimized TCB process. With 0.05W pumping power for the micro-cooler, the heat dissipation capability of 260W/cm2 has been demonstrated, and the chip temperature can be maintained under 51°C. Excellent agreement has been obtained between experimental and simulation results. With the MDMT, fully developed jet impingement can be achieved for each nozzle, and uniform chip temperature distribution is obtained.

Thermal management solutions and design guidelines for silicon based photonic integrated modules

In this study, thermal design and thermal management for a low-cost photonic integrated circuits (PIC) platform is proposed and analyzed. The involved PIC platform is targeted for various applications including optical communications, optical interconnects, signal processing and sensing. The module considered in this study consists of a rigid PCB made of FR4 material and a silicon photonics ICs platform on which a laser diode chip, a driver chip, and a trans-impedance amplifier (TIA) chip are jointed using solder balls. A kovar case is chosen for the module. For the thermal design and thermal management, two objectives are involved in this study. The first one is to reduce the thermal resistance from junction to ambient and the other one is to reduce the thermal cross talk between the driver/TIA chips and laser source chip. The following accomplishments are achieved in this study. The overall junction to ambient thermal resistance is reduced to a certain level and meets the design target. The thermal cross effect between the driver/TIA chips and the laser source chip is reduced by cutting a slot in the silicon photonic platform and implementing separated heat spreaders for these chips.

An efficient single phase liquid cooling system for microelectronic devices with high power chip

In this study, an efficient single phase liquid cooling system with the heat dissipation capability of 350 W/cm2 on a chip of 7mm × 7mm (a total power of 175 W) under the pumping power of 0.1 W is developed and examined. Such a liquid cooling system is proposed for the microelectronic devices with high power chip such as the high performance servers and power amplifies. Our focus in this study is on the efficiency improvement of both the micro-cooler and heat exchanger, which are the major contributors of the full liquid cooling system performance. The accomplishments include the development of the silicon based hybrid micro-cooler combining the merits of both micro-jet array impingement and micro-channel flow cooling technologies and the optimization of the miniaturized heat exchanger with low pressure drop, small footprint area and high heat exchange efficiency.

Micro-channel heat sink with multiple interactive pressure-driven or electro-osmotic flows

A micro-channel heat sink with multiple interactive pressure-driven or electro-osmotic flows is developed for the thermal management of electron devices with high power density. Several structures have been designed, which will enable high heat dissipation capability, even temperature distribution and low driving pressure/electric field. This thermal solution shows enhanced cooling capability not only in dissipating the uniform heat flux but also in diminishing the localized hot spots for the electric devices. For the new heat sink structure of larger hydraulic diameter with pressure-driven flow, the thermal resistance can be decreased by 65% compared with the regular structure. With the same operating flow rate, the proposed structure enables 80% decrease of the pressure drop in addition to about 25% improvement of the thermal resistance. For the new structure of smaller hydraulic diameter with electro-osmotic flow, the thermal resistance is highly reduced, and about 45% improvement can be obtained. With the same flow rate, the electric voltage can be decreased by about 50%. More even temperature distribution can be obtained by using the new heat sink for hot spots cooling.