Boon Long Lau

Enhancement of Hotspot Cooling With Diamond Heat Spreader on Cu Microchannel Heat Sink for GaN-on-Si Device

The diamond heat spreader has been directly attached between the test chip and the Cu microchannel heat sink for thermal performance enhancement of the GaN-on-Si device. In the fabricated test vehicle, the small heater is used to represent one unit of transistor. Experimental tests have been conducted on the fabricated test vehicle to investigate the performance. Two types of simulation models have been constructed in COMSOL, considering the multiphysics features and temperature-dependent material properties. The submodel in conjunction with the main model is constructed to predict the thermal performance of the GaN-on-Si structure. The heating power, which is concentrated on eight tiny heaters of size 350 × 150 μm2, is varied from 10 to 50 W. With the diamond heat spreader attached to the liquidcooled microchannel heat sink, the maximum heater temperature can be reduced by 11.5%-22.9%, while the maximum gate temperature can be reduced by 8.9%-18.5%. Consistent results from the experimental and simulation studies have verified the enhancement of the hotspot cooling capability using directly attached diamond heat spreader.

TSV Cu Filling Failure Modes and Mechanisms Causing the Failures

In this paper, we report through-silicon via (TSV) Cu filling failure modes and categorize them into three major regions based on their causes. First, Si etch-related region for the TSV defining. Si etch defects, such as bottom corner notch, Si grass at the bottom, surface roughness, and sponge-like defect, cause Cu seed layer loss at the defect areas. It causes electrical disconnection resulting in the TSV Cu filling failure. Second, Cu seed layer-related region. Defects include poor Cu seed layer step coverage and oxidation of the Cu seed layer from the Cu seed layer deposition until the TSV Cu electroplating from the Cu seed layer deposition. They result in aggrandizing terminal effect, which makes Cu ion reduction at the TSV bottom difficult. Third, Cu electroplating-related region. The most important factor in this region is chemical concentration control because the TSV Cu filling by bottom up filling mainly depends on the cooperation of three additives of suppressor, accelerator, and leveler. Another important factor in the region is current density ramp up rate. It is critical to ramp up the current density with an appropriate rate to prevent pinchoff plating causing voids inside the TSVs. These regions are closely connected with each other and the relationship needs to be understood to overcome the TSV Cu filling failure.

Thermal Characterization of Both Bare Die and Overmolded 2.5-D Packages on Through Silicon Interposers

The next generation of heterogeneous integration requires 2.5-D packages on through silicon interposer (TSI) as enabling technology for less signal delay, faster speed, and more functionality. In the meantime, the introduction of multiple chips on interposer tends to increase the heat density with added interconnect complexity, which requires systematic thermal analysis and characterization. In this paper, thermal characterization of 2.5-D packages on TSI is reported in both bare-die package and overmolded package formats. The test vehicle consists of two dummy chips and thermal test die assembled on the same interposer of 18 mm × 18 mm × 0.1 mm through the flip chip bumping and joining process. A thermal test chip of 5.08 mm × 5.08 mm is built in with heaters and diodes for thermal characterization. Thermal measurements are conducted for thermal resistances from junction to the ambient, from junction to the board, and from junction to top casing. Measurement accuracy is improved through distributed through silicon via network, multidie temperature monitoring and uncertainty analysis and minimization. It is found that the overmolded package has lower thermal resistances than the bare die package. In addition, the thermal resistance from the junction to the casing is also characterized with a liquid-cooled minichannel cold plate as heat sink, indicating the vast difference between bare die package and molded package. Besides experimental measurements, thermal simulation models under different boundary conditions are established, respectively, to compare with the measurements. Good agreements are generally achieved between simulation and measurements. Further simulation is also conducted to examine the effects of overmold thickness and power dissipation from the multichips module on the interposer.

Thermal Management of Hotspots With a Microjet-Based Hybrid Heat Sink for GaN-on-Si Devices

The direct-die-attached cooling solution with a diamond heat spreader and hybrid Si heat sink has been developed for hotspot cooling of a GaN-on-Si device. The hybrid heat sink combines the benefits of microchannel flow and microjet impingement. In the fabricated test chip, the small hotspot is used to represent one unit of a GaN transistor. Experimental tests have been conducted on the fabricated test vehicle to investigate the thermal and fluidic performances. Two types of simulation models have been constructed using the commercial Finite Element Method software COMSOL, using the multiphysics features and temperature-dependent material properties. A submodel in conjunction with the main model is constructed to predict the thermal performance of the GaN-on-Si structure. Various heating powers 10-150 W are loaded on eight tiny hotspots of size 450 × 300 μm (heat flux on each hotspot 0.93-13.89 kW/cm2). An overall spatially averaged heat transfer coefficient of 11.53 × 104 W/m2K has been achieved in the microjet-based hybrid heat sink. Consistent results from the experimental and simulation studies have verified the high heat dissipation capability of the designed cooling solution. Several simulations have been conducted to investigate the effects of the heat sink structure and dimensions on the performances for hotspot thermal management.

Package-Level Microjet-Based Hotspot Cooling Solution for Microelectronic Devices

A package-level hotspot cooling solution using Si hybrid heat sink and diamond heat spreader has been developed. The hybrid heat sink combines the merits of both microchannel flow and microjet array impingement, and can enable high spatially average heat transfer coefficient of 18.9 × 104 W/m2 K with low pumping power of 0.17 W. The liquid jet is designed to directly impinge on the surface of the diamond heat spreader. The eight hotspot heaters, each of size 450 × 300 μm2, were fabricated on the Si thermal test chip. The solid-fluid coupling simulation has been conducted using heaters model for microfluid cooling capability investigation. A gates model in conjunction with the heaters model is used to predict the thermal performance of the GaN transistors with the developed cooling solution. Hotspot cooling capability as high as 10 kW/cm2 was demonstrated and validated. The heating power density of 3.9 W/mm can be dissipated in GaN device, while maintaining the peak gate temperature under 200°C.

Thermal characterization and simulation study of 2.5D packages with multi-chip module on through silicon interposer

Next generation of heterogeneous integration requires 2.5D package on interposer as enabling technology for less signal delay, faster speed, and more functionality. In this work, thermal characterization and simulation of a 2.5D package with multi chips on through silicon interposer (TSI) are reported. Two dummy chips with chip sizes of 7.6×10.9mm and 8mm×8mm, respectively, are arranged on the interposer through the flip chip bumping and joining process. To facilitate the thermal characterization, a thermal test chip of 5.08×5.08mm is embedded on the same interposer for thermal test and simulation validation. In either molded or bare die BGA package format, the thermal test vehicles are brought for thermal characterization, including Theta JA Theta JB measurement conforming with the JEDEC standards. It is found that the overmolded package has slightly lower thermal resistances than the bare die package. In addition, the Theta JC, namely, the thermal resistance from the junction to the top casing is also characterized through a high performance cold plate. Besides the thermal measurements, thermal simulation models under different boundary conditions are established, respectively, to compare with the thermal measurements. Good agreements are generally achieved between simulation and measurements. Further simulation is also conducted to study the effects of overmold thickness and power dissipation from the multi chips module on the interposer.

Thermal Management of Hotspots Using Diamond Heat Spreader on Si Microcooler for GaN Devices

A diamond heat spreader has been applied on the hybrid Si microcooler for the improvement of the hotspots cooling capability for GaN devices. The microwave chemical vapor deposition diamond heat spreader under tests is of thickness 400 μm and thermal conductivity as high as 1500 ~ 2000 W/mK, and is bonded through the thermal compression bonding process at chip level. Eight hotspots, each of size 450 × 300 μm2, were fabricated on a Si thermal test chip to mimic the heating areas of eight GaN units. Heat dissipation capabilities were studied and compared through experimental tests and thermal/fluid simulations, and consistent results have been obtained. Using the diamond heat spreader, to dissipate 70-W heating power, the maximum chip temperature can be reduced by 40.4% and 27.3%, compared with the structure without a heat spreader and the one with a copper heat spreader, respectively. While maintaining the maximum hotspot temperature under 160°C, 10-kW/cm2 hotspot heat flux can be dissipated. The thermal effects of the heat spreader thickness, the diamond thermal conductivity, and the bonding layer are investigated. Based on the simulation results, the higher power density of the GaN device can be dissipated, while maintaining the peak gate temperature under 200°C. The concentrated heat flux has been effectively reduced using a diamond heat spreader, and much better cooling capability of the Si microcooler has been achieved for high-power GaN devices.

Development of package level hybrid silicon heat sink for hotspots cooling

In this paper, the fabrication of package level silicon microchannel heat sink for hotspot thermal management is presented. These include the design, micro fabrication process and chip level integration of a hybrid silicon heat sink, which integrates jet impingement, microchannel cooling technologies. The fabrication of hybrid heat sink is proposed by bonding two Si chips which patterned with nozzle and microchannel structures separately. The nozzle array is fabricated using though silicon vias (TSV) process. This nozzle plate is used to generate jet impingement effect into the microchannel heat sink. On the other hand, the microchannel heat sink consists of micro fins and channels which are fabricated using deep reactive ion etch (DRIE) process. The micro fins increase the area for convective heat transfer while the micro channels serve as the liquid conduit to carry the intense heat away from the heat source. Two silicon chips are bonded using thermal compression bonding (TCB) process. For the packaging, the integration of thermal chip and diamond heat spreader onto silicon heat sink is performed using gold-tin eutectic bonding through TCB process. In this paper, the major fabrication steps and critical process parameters will be discussed in details along with the hydraulic test and thermal analysis.

Development of fluxless bonding using deposited Gold-indium multi-layer composite for heterogeneous silicon micro-cooler stacking

In this paper, Gold-indium fluxless eutectic bonding at short process time has been successfully developed for stacking multi-layers and heterogeneous structure of silicon micro-cooler. This paper introduces gold-indium eutectic bonding process which uses deposited thin and multilayer composites directly onto the silicon surfaces which to be bonded. The parameters DOE (design of experiment) study was carried out to develop thermal compression bonding process conditions as tabulated in Table 1. These eutectic bonds are examined using shear test, Scanning Electron Microscope (SEM) and Energy Dispersive X-ray Spectroscopy (EDX). This shear test results is compared with eutectic AuSn which is best known as hard solders, good fatigue-resistance and mechanical properties. Nearly void-free bonds are achieved and confirmed by cross-sectional SEM and X-ray scanning. A pre-clean process steps is required to ensure sufficient wetting and good adhesion for this fluxless process. Furthermore, a thermal cycling test and Scanning Acoustic Microscope (SAM) analysis will be carried out to evaluate the failure mode, reliability of solder joint and the bonded structure.

Si-Based Hybrid Microcooler With Multiple Drainage Microtrenches for High Heat Flux Cooling

Microfluid cooling solution is one of the most effective techniques for thermal management of high heat fluxes. A jet-based Si microcooler with multiple drainage microtrenches (MDMTs) has been developed for microelectronic thermal management. Integrated with MDMT in hybrid microcooler, the negative cross-flow effect between nearby nozzles is eliminated, and thus fully developed jet impingement can be enabled for each nozzle. An inlet/outlet flow arrangement layer has been introduced to achieve uniform pressure distribution. The effects of three types of arrangement structures on the hydraulic and thermal performance of microcooler have been analyzed and compared. Two different thermal/fluid simulation models have been constructed for microcooler design. The test vehicle with the new nozzle/trench layer is fabricated using double-side deep reactive-ion etching process. Assembly of the stacked microcooler and Si thermal test chip is finished through two-steps optimized thermal compression bonding process. With 0.05-W pumping power for the microcooler, the heat dissipation of 260 W/cm2 has been demonstrated, and the chip temperature can be maintained under 51 °C. Excellent agreement has been obtained between experimental and simulation results. With the MDMT, enhanced-microjet array impinging has been achieved, and uniform chip temperature distribution is obtained.