Xinyu Bao

Low defect InGaAs quantum well selectively grown by metal organic chemical vapor deposition on Si(100) 300 mm wafers for next generation non planar devices

Metal organic chemical vapor deposition of GaAs, InGaAs, and AlGaAs on nominal 300 mm Si(100) at temperatures below 550 °C was studied using the selective aspect ratio trapping method. We clearly show that growing directly GaAs on a flat Si surface in a SiO2 cavity with an aspect ratio as low as 1.3 is efficient to completely annihilate the anti-phase boundary domains. InGaAs quantum wells were grown on a GaAs buffer and exhibit room temperature micro-photoluminescence. Cathodoluminescence reveals the presence of dark spots which could be associated with the presence of emerging dislocation in a direction parallel to the cavity. The InGaAs layers obtained with no antiphase boundaries are perfect candidates for being integrated as channels in n-type metal oxide semiconductor field effect transistor (MOSFET), while the low temperatures used allow the co-integration of p-type MOSFET.

Anti-phase boundaries–Free GaAs epilayers on “quasi-nominal” Ge-buffered silicon substrates

We have obtained Anti-Phase Boundary (APB) free GaAs epilayers on “quasi-nominal” (001) silicon substrates, while using a thick germanium strain relaxed buffer between the GaAs layer and the silicon substrate in order to accommodate the 4% lattice mismatch between the two. As silicon (001) substrates always have a small random offcut angle from their nominal surface plane, we call them “quasi-nominal.” We have focused on the influence that this small (≤0.5°) offcut angle has on the GaAs epilayer properties, showing that it greatly influences the density of APBs. On 0.5° offcut substrates, we obtained smooth, slightly tensile strained (R = 106%) GaAs epilayers that were single domain (e.g., without any APB), showing that it is not necessary to use large offcut substrates, typically 4° to 6°, for GaAs epitaxy on silicon. These make the GaAs layers more compatible with the existing silicon manufacturing technology that uses “quasi-nominal” substrates.

Toward the III–V/Si co-integration by controlling the biatomic steps on hydrogenated Si(001)

The integration of III-V on silicon is still a hot topic as it will open up a way to co-integrate Si CMOS logic with photonic devices. To reach this aim, several hurdles should be solved, and more particularly the generation of antiphase boundaries (APBs) at the III-V/Si(001) interface. Density functional theory (DFT) has been used to demonstrate the existence of a double-layer steps on nominal Si(001) which is formed during annealing under proper hydrogen chemical potential. This phenomenon could be explained by the formation of dimer vacancy lines which could be responsible for the preferential and selective etching of one type of step leading to the double step surface creation. To check this hypothesis, different experiments have been carried in an industrial 300 mm metalorganic chemical vapor deposition where the total pressure during the annealing step of Si(001) surface has been varied. Under optimized conditions, an APBs-free GaAs layer was grown on a nominal Si(001) surface paving the way for III...

Ultrathin InAs-channel MOSFETs on Si substrates

Planar ultrathin InAs-channel MOSFETs were demonstrated on Si substrates with gate lengths (Lg) as small as 20 nm. The III-V epitaxial buffer layers were grown on 300 mm Si substrates by metal-organic chemical vapor deposition (MOCVD) and the subsequent InAlAs bottom barriers and InAs channel were grown by molecular beam epitaxy (MBE). The devices at 20 nm Lg show high transconductance, ~2.0 mS/μm at VDS=0.5V.

Electrical Characterization of GaP-Silicon Interface for Memory and Transistor Applications

Process conditions of gallium phosphide (GaP) metal-organic chemical vapor deposition growth on silicon (Si) are optimized by material characterization. Thorough investigation of GaP-Si interface at this optimized growth condition is carried out by electrical characterization with the perspective of applying this heterostructure system for improving the performance of logic transistors and retention time of capacitorless single-transistor dynamic RAM (1T-DRAM). Fabricated GaP-Si heterojunction diodes exhibit an ON-OFF ratio of 108 with similar reverse current as the ideal device simulation results signify immunity to the existing antiphase domains. Finally, MOSFET devices with GaP source-drain having subthreshold swing of 70 mV/dec and an ON-OFF ratio of 105 are demonstrated.

Improvement of Si doping of In 0.53 Ga 0.47 As fin by heated implant

III-V materials are candidates for high mobility channel and low contact resistance SD at 5nm technology node and beyond [1]. Traditional Si+ ion implant of In0.53Ga0.47As at room temperature causes amorphization of fin and formation of stacking fault defects upon activation anneal. We have demonstrated heated implant can eliminate amorphization induced crystalline damages and improve fin conductance.

The Effect of Interfacial Contamination on Antiphase Domain Boundary Formation in GaAs on Si(100)

The suppression of defects such as antiphase domain boundaries (APBs) is a key challenge in the effort to integrate III-V compound semiconductor devices on Si. The formation of APBs naturally arises from growing a polar material on a nonpolar substrate. Surface contamination present on the substrate prior to growth can also disrupt the ordering of atoms in an epitaxial layer and lead to extended defects. In this study, the amount of contamination on Si(100) wafers was varied by approximately an order of magnitude to investigate the effect on formation of APBs in an epitaxial GaAs film grown by MOCVD. The results indicate a direct correlation between the interfacial oxygen and carbon impurity dose and the APB density.

GaP source-drain vertical transistor on bulk silicon for 1-transistor DRAM application

GaP is proposed as source and drain material for 1-transistor DRAM application as it is nearly lattice matched to silicon and provides a valence band offset of ~ 1 eV. Simulations of retention time for the proposed vertical structure indicate: large improvement over similar bulk silicon devices, ability to meet ITRS requirement and good scalability. An MOCVD recipe is optimized for GaP growth on silicon and further characterized by fabricating electrical devices such as diodes and transistors indicating feasibility for usage in 1T-DRAM technology.

GaP source-drain SOI 1T-DRAM: Solving the key technological challenges

SOI based GaP source drain 1T DRAM with silicon channel is proposed. Using BJT-latch based programing, it is shown that the scalability of GaP-SD 1T-DRAM can be extended up to 20nm. Nickel alloying of GaP is proposed as a method to reduce the sheet and contact resistance of GaP source and drain. Using nickel alloying, the ON-current of the GaP-SD transistor is improved by an order and the proper scalability behavior is established.