Zhiyuan Ye

A study of low energy phosphorus implantation and annealing in Si:C epitaxial films

The effect of phosphorus implantation and thermal annealing on properties of Si:C epitaxial films was investigated. High resolution x-ray diffraction analysis and secondary ion mass spectroscopy indicated that spike annealing only causes slight loss of substitutional carbon. Phosphorus implantation, even with low energy, could cause surface damages and loss of substitutional carbon. Although spike annealing effectively activates implanted phosphorus, it also results in significant substitutional carbon loss (from 1.2% to less than 0.5%) within the phosphorus diffused layer. The interaction of carbon and phosphorus resulted in a junction profile as abrupt as with 3 nm/decade.

Heavily Phosphorus Doped Silicon Junctions for nMOS Applications

Epitaxially grown Silicon Carbon (Si:C) in recessed junction regions has been shown to induce tensile stress in the nMOS channel and thereby enhance the transistor performance. In addition to the stress induced in the channel, this technology also needs to achieve low resistivity junctions for widespread use. This work discusses epitaxially grown heavily doped Si/ Si:C layers which can be used in nMOS junctions and can address both these requirements. Si:C epitaxial layers are shown to have phosphorus concentrations as high as 1.25 X 10^21 cm^-3 with resistivities as low as 0.3 mOhm.cm. Applications of these layers can range from Si:P cap layers for low series resistance to Si:PC layers for inducing stress in the nMOS channel.

Ultrathin InAs-channel MOSFETs on Si substrates

Planar ultrathin InAs-channel MOSFETs were demonstrated on Si substrates with gate lengths (Lg) as small as 20 nm. The III-V epitaxial buffer layers were grown on 300 mm Si substrates by metal-organic chemical vapor deposition (MOCVD) and the subsequent InAlAs bottom barriers and InAs channel were grown by molecular beam epitaxy (MBE). The devices at 20 nm Lg show high transconductance, ~2.0 mS/μm at VDS=0.5V.

Electrical Characterization of GaP-Silicon Interface for Memory and Transistor Applications

Process conditions of gallium phosphide (GaP) metal-organic chemical vapor deposition growth on silicon (Si) are optimized by material characterization. Thorough investigation of GaP-Si interface at this optimized growth condition is carried out by electrical characterization with the perspective of applying this heterostructure system for improving the performance of logic transistors and retention time of capacitorless single-transistor dynamic RAM (1T-DRAM). Fabricated GaP-Si heterojunction diodes exhibit an ON-OFF ratio of 108 with similar reverse current as the ideal device simulation results signify immunity to the existing antiphase domains. Finally, MOSFET devices with GaP source-drain having subthreshold swing of 70 mV/dec and an ON-OFF ratio of 105 are demonstrated.

Application of Selective Si:C Epitaxy For Recessed Source/Drain Technology

INTRODUCTION It is understood that a uniaxial tensile stress along a channel of transistor enhances electron mobility and drive current of NMOS transistors. Typically, a tensile stress-enhanced silicon nitride layer is used to strain the channel [1]. For even further enhancement of transistor drive current, a use of silicon carbon alloy (Si:C) in recessed source/drain (S/D) area has been considered. Alloying Si with C decreases lattice parameters when carbon atoms occupy substitutional sites of Si lattices. Very recently, it has been reported that a use of Si:C epitaxy in recessed S/D generates tensile strain in the channel of NMOS transistor and consequently increases transistor drive current [2]. The Si:C recessed S/D technology has two major challenges in preparing an epitaxy solution: One is how to incorporate carbon atoms into substitutional sites. As the solid solubility of substitutional carbon in silicon is only ~10 cm, carbon atoms at concentrations higher than this easily incorporate into interstitial sites or precipitate as β-SiC, resulting in no strain in the epilayer. Therefore, in order to achieve high substitutional carbon concentration (≥ 1%) with minimizing interstitial carbon concentration, non-equilibrium epitaxial growth conditions such as low temperature (≤ 600 C) are required [3]. The other is to obtain selectivity and reasonable growth rate of selective Si:C epitaxy process with maintaining high substitutional carbons. We have developed selective Si:C epitaxy processes with 1% or higher substitutional carbon concentration and will discuss characteristics of the epitaxy grown on recessed area of patterned wafers.

Integrating Selective Epitaxy in Advanced Logic & Memory Devices

INTRODUCTION Selective epitaxy has gained increasing momentum in advanced high-performance logic as well as volatile and nonvolatile memory device fabrication. The advantages of this technique range from the well documented application of strained SiGe epitaxial films used to increase hole mobility and performance in pFET devices to intrinsic Si epitaxial layers used to prevent short channel effects in memory devices (DRAM). Other applications call upon the time tested strengths of epitaxy in ensuring abrupt, activated doped layers or junctions without the defectivity associated with implanted profiles.

The Effect of Interfacial Contamination on Antiphase Domain Boundary Formation in GaAs on Si(100)

The suppression of defects such as antiphase domain boundaries (APBs) is a key challenge in the effort to integrate III-V compound semiconductor devices on Si. The formation of APBs naturally arises from growing a polar material on a nonpolar substrate. Surface contamination present on the substrate prior to growth can also disrupt the ordering of atoms in an epitaxial layer and lead to extended defects. In this study, the amount of contamination on Si(100) wafers was varied by approximately an order of magnitude to investigate the effect on formation of APBs in an epitaxial GaAs film grown by MOCVD. The results indicate a direct correlation between the interfacial oxygen and carbon impurity dose and the APB density.

GaP source-drain vertical transistor on bulk silicon for 1-transistor DRAM application

GaP is proposed as source and drain material for 1-transistor DRAM application as it is nearly lattice matched to silicon and provides a valence band offset of ~ 1 eV. Simulations of retention time for the proposed vertical structure indicate: large improvement over similar bulk silicon devices, ability to meet ITRS requirement and good scalability. An MOCVD recipe is optimized for GaP growth on silicon and further characterized by fabricating electrical devices such as diodes and transistors indicating feasibility for usage in 1T-DRAM technology.

GaP source-drain SOI 1T-DRAM: Solving the key technological challenges

SOI based GaP source drain 1T DRAM with silicon channel is proposed. Using BJT-latch based programing, it is shown that the scalability of GaP-SD 1T-DRAM can be extended up to 20nm. Nickel alloying of GaP is proposed as a method to reduce the sheet and contact resistance of GaP source and drain. Using nickel alloying, the ON-current of the GaP-SD transistor is improved by an order and the proper scalability behavior is established.

A Study of Low Energy Phosphorus Implantation and Annealing in Si:C Epitaxial Films

We investigated the effect of dopant implantation and thermal annealing on substitution carbon concentration of Si:C epitaxial film. While spike annealing at T=1050 degC results in slight loss of substitution carbon (0.6%) but maintains high crystalline, phosphorus implantation induces significant loss of substitution carbon and a change of carbon depth profile. It is also observed that very abrupt junction can be formed in a Si:C epitaxial film