Sri Harsha Choday

A Three-Terminal Dual-Pillar STT-MRAM for High-Performance Robust Memory Applications

The design of a three-terminal self-aligned dual-pillar (DP) magnetic tunnel junction (MTJ) utilizing both current-induced spin-transfer torque (STT) and magnetic domain-wall motion effects is proposed for high-speed nonvolatile robust memory applications. The choice of a thin tunneling oxide (~0.9 nm) in a write-in port, spatially and electrically separated from a read-out port incorporating a thicker (~1.8 nm) oxide on an extended thin-film multilayer stack, significantly improves the overall cell stability and parametric process yield of a memory array. A dual-bit-line memory architecture incorporating a single-ended voltage-sensing scheme for fast data readout with just one access transistor per cell is also proposed for the first time. The technology-circuit cooptimization of the proposed single-transistor (1T) DP STT magnetic random access memory (MRAM) cell is carried out using effective mass-based transport simulations in nonequilibrium Greens function formalism and accurate micromagnetic simulations involving the Landau-Lifshitz-Gilbert-Slonczewski equation. The proposed DP STT-MRAM bit cell outperforms a state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell tunneling magnetoresistance, simplified memory array architecture with a single supply for read/write, and significantly lower probability of disturb and access failures under parametric process variations with a marginal increase in critical switching current.

KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells

The storage device in spin-transfer torque MRAM (STT-MRAM) is the magnetic tunneling junction (MTJ) and several models for the MTJ have been proposed. However, a simulation framework that captures device physics at the atomistic level when simulating STT-MRAM at the bit-cell level is lacking. We propose a simulation framework (KNACK) which models the MTJ at the atomistic level using the Non-Equilibrium Greens Function (NEGF) formalism and uses the NEGF model in conjunction with our STT-MRAM bit-cell circuit model for circuit-level simulations. Our simulation framework accepts I–V and C-V characteristics of the access device input either as lookup tables or as compact models. We show that with appropriate device and bit-cell parameters, our simulation framework has the ability to capture MTJ physics and simulate different genres of STT-MRAM bit-cells with results in agreement with experiments.

Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching

Spin-transfer torque magnetic random access memories (STT-MRAM), using magnetic tunnel junctions (MTJ), is a resistive memory technology that has spurred significant research interest due to its potential for on-chip, high-density, high-speed, low-power, and non-volatile memory. However, due to conflicting read and write requirements, there is a need to develop optimization techniques for designing STT-MRAM bit-cells to minimize read and write failures. We propose an optimization technique that minimizes read and write failures by proper selection of bit-cell configuration and by proper access transistor sizing. A mixed-mode simulation framework was developed to evaluate the effectiveness of our optimization technique. Our simulation framework captures the transport physics in the MTJ using Non-Equilibrium Greens Function method and self-consistently solves the MTJ magnetization dynamics using Landau-Lifshitz-Gilbert equation augmented with the full Slonczewski spin-torque term. The electrical parameters of the MTJ are then encapsulated in a Verilog-A model and used in HSPICE to perform bit-cell level optimization. The optimization technique is applied to STT-MRAM bit-cells designed using 45 nm bulk and 45 nm silicon-on-insulator CMOS technologies. Finally, predictions are made for optimized STT-MRAM bit-cells designed in 16 nm predictive technology.

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells

The emergence of spin-transfer torque magnetic RAM (STT-MRAM) as a leading candidate for future high-performance nonvolatile memory has led to increased research interest. Current STT-MRAM technology faces several major obstacles in attaining its potential. One of the major issues is in the design of 1T-1MTJ STT-MRAM bit-cells under process variations: the bit-cells need to be significantly upsized to improve bit-cell failure, resulting in increased bit-cell area and power dissipation. In this paper, we analyze four circuit-level solutions that enable smaller 1T-1MTJ STT-MRAM bit-cells with improved yield, namely, bit-line voltage boosting, word-line voltage boosting, access transistor body biasing, and an applied external magnetic field. Results from simulation using 45-nm bulk CMOS access transistor and 40-nm magnetic tunneling junction technology show that word-line voltage boosting can be the best failure mitigation technique. Bit-cells designed with word-line boosting for write has a bit-cell area reduced by > 75% at iso-failure probability, compared to bit-cells without any failure mitigation technique. When bit-cell failure probability is optimized instead, 5 Oe of applied external magnetic field assisted write reduces power consumption by 15% , compared to bit-cells designed without failure mitigation techniques.

Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective

Electron-spin based data storage for on-chip memories has the potential for ultrahigh density, low power consumption, very high endurance, and reasonably low read/write latency. In this article, we analyze the energy-performance characteristics of a state-of-the-art spin-transfer-torque based magnetic random access memories (STT-MRAM) bit-cell in the presence of parametric process variations. In order to realize ultra low power under process variations, we propose device, bit-cell and architecture level design techniques. Such design methods at various levels of design abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.

Loihi: A Neuromorphic Manycore Processor with On-Chip Learning

Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon. It integrates a wide range of novel features for the field, such as hierarchical connectivity, dendritic compartments, synaptic delays, and, most importantly, programmable synaptic learning rules. Running a spiking convolutional form of the Locally Competitive Algorithm, Loihi can solve LASSO optimization problems with over three orders of magnitude superior energy-delay-product compared to conventional solvers running on a CPU iso-process/voltage/area. This provides an unambiguous example of spike-based computation, outperforming all known conventional solutions.

DSH-MRAM: Differential Spin Hall MRAM for On-Chip Memories

A new device structure for spin-transfer torque-based magnetic random access memory (STT-MRAM) is proposed for on-chip memory applications. Our device structure exploits spin Hall effect to create a differential memory cell that exhibits fast and energy-efficient write operation. In addition, because of inherently differential device structure, fast and reliable read operation can be performed. Our simulation study shows 10× improvement in write energy over the standard 1T1R in-plane STT-MRAM memory cell, and 1.6× faster read operation compared with single-ended sensing (as in standard 1T1R STT-MRAMs). The bit-cell characteristics are promising for high performance on-chip memory applications.

SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture

A novel nonvolatile flip-flop (NVFF) using a magnetic tunnel junction (MTJ) is presented for power gating architecture. The proposed NVFF exploits spin Hall effect (SHE) for fast and low-power data backup into MTJs before the power is gated off. Owing to the high spin injection efficiency of SHE, the estimated write current for backup operation is lower than 40 μA. Due to the low write current requirement, we do not introduce a dedicated write driver circuit. Instead, we utilize the cross-coupled inverters in the slave latch to perform the backup operation, resulting in low area overhead. The simulation results show 10× improvement in backup energy when compared with previous works on spin transfer torque-based NVFFs.

SPIN ORBIT TORQUE BASED ELECTRONIC NEURON

A device based on current-induced spin-orbit torque (SOT) that functions as an electronic neuron is proposed in this work. The SOT device implements an artificial neurons thresholding (transfer) function. In the first step of a two-step switching scheme, a charge current places the magnetization of a nano-magnet along the hard-axis, i.e., an unstable point for the magnet. In the second step, the SOT device (neuron) receives a current (from the synapses) which moves the magnetization from the unstable point to one of the two stable states. The polarity of the synaptic current encodes the excitatory and inhibitory nature of the neuron input and determines the final orientation of the magnetization. A resistive crossbar array, functioning as synapses, generates a bipolar current that is a weighted sum of the inputs. The simulation of a two layer feed-forward artificial neural network based on the SOT electronic neuron shows that it consumes ∼3× lower power than a 45 nm digital CMOS implementation, while reaching ∼80% accuracy in the classification of 100 images of handwritten digits from the MNIST dataset.

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

Spin-transfer torque magnetic RAM (STT-MRAM) is a promising memory technology for lower level caches because of its high density and nonvolatile nature. However, the high write latency is a bottleneck to its widespread adoption as the future on-chip memory. In this paper, we propose a new cache architecture-asymmetric write architecture with redundant blocks (AWARE)-that can improve the write latency by taking advantage of the asymmetric write characteristics of 1T-1MTJ STT-MRAM bit-cells. Due to the nature of the storage element in STT-MRAM, the time required for the two-state transitions ( 1→ 0 and 0→ 1) is not identical. In other words, one of the state transitions is slower than the other direction. In conventional cache architecture, the overall write latency is limited by the slower transition. However, the AWARE cache design introduces redundant blocks in each row, and they are preset to the initial state that enables the faster transition. Hence the write operations performed in these redundant blocks are much faster than the conventional write scheme. The write latency in AWARE is improved by 30% over conventional cache architecture with no area penalty in the data array. Moreover, the additional tag bits introduced in this technique result in penalty on the total cache area. In addition, the write energy increases modestly by 7% in the proposed cache design. However, this write-energy increase can be mitigated by sacrificing the cache capacity.