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Featured researches published by Y.C. Cheng.
IEEE Transactions on Electron Devices | 1993
Zhihong Liu; Chenming Hu; Jian-Hui Huang; Tung-Yi Chan; Min-Chie Jeng; Ping Keung Ko; Y.C. Cheng
The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >
IEEE Electron Device Letters | 1990
K.K. Hung; P.K. Ko; C. Hu; Y.C. Cheng
The random telegraph noise exhibited by deep-submicrometer MOSFETs with very small channel area (<or=1 mu m/sup 2/) at room temperature is studied. Analysis of the amplitude of the current fluctuations reveals that the trapped charges generate noise through modulation of the carrier mobility in addition to the carrier number. Parameters needed for modeling the carrier mobility fluctuation effect on the flicker noise in conventional MOSFETs are extracted directly from the random telegraph noise data.<<ETX>>
IEEE Electron Device Letters | 1994
Zhi-Jian Ma; James C. Chen; Z.H. Liu; J. T. Krick; Y.C. Cheng; C. Hu; P.K. Ko
It has been reported that high-temperature (/spl sim/1100/spl deg/C) N/sub 2/O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900/spl sim/950/spl deg/C) N/sub 2/O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO/sub 2/ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60/spl sim/110 /spl Aring/ gate oxides, a certain amount of nitrogen (/spl sim/2.2%) incorporated near the Si/SiO/sub 2/ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate.<<ETX>>
IEEE Electron Device Letters | 1994
Zhi-Jian Ma; H.J. Wann; Mansun Chan; Joe King; Y.C. Cheng; Ping Keung Ko; Chenming Hu
Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E/sub m/). Experimental results using SOI MOSFETs with body contacts indicate that E/sub m/ is just a weak function of thin-film SOI thickness (T/sub si/ and that E/sub m/ can be significantly lower than in a bulk device with drain junction depth (X/sub j/) comparable to SOIs T/sub si/. The theoretical correlation between SOI MOSFETs gate current and substrate current are experimentally confirmed. This provides a means (I/sub G/) of studying E/sub m/ in SOI device without body contacts. Thin-film SOI MOSFETs have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought.<<ETX>>
IEEE Electron Device Letters | 1992
Z.H. Liu; Hsing-Jen Wann; Ping Keung Ko; Chenming Hu; Y.C. Cheng
The effects of post-oxidation N/sub 2/O anneal on conventional thermal oxide are studied. The oxide thickness increase resulting from N/sub 2/O anneal is found to be self-limiting and insensitive to initial oxide thickness, which makes the thickness of the resulting oxide easy to control. The N/sub 2/O anneal leads to increased resistance against injection-induced interface-state generation and to reduced hole trapping. No further quality improvement is found when the N/sub 2/O-annealed oxide is subject to an additional reoxidation. This finding confirms that nitrogen incorporation in the absence of hydrogen is responsible for improving the quality of the conventional oxides.<<ETX>>
IEEE Transactions on Electron Devices | 1994
Z. J. Ma; Zhihong Liu; Y.C. Cheng; Ping Keung Ko; Chenming Hu
The mobility crossover phenomenon observed in NH/sub 3/-nitrided N-MOSFETs has been interpreted by the reduced acceptor-type interface states which are located near and above the conduction band edge. However. A direct confirmation of such a hypothesis is not available from the conventional electrical measurement techniques. In this work, for the first time, we used both 1/f noise and random telegraph signal (RTS) measurements which are capable of probing those oxide traps near and above Si conduction band of energy, to study the modification of interface traps induced by N/sub 2/O nitridation. The 1/f noise measurement results confirm that thermal nitridation decreases the near-interface oxide trap density at the higher energy levels, as a result, trapping of the mobile electrons is decreased. The RTS measurement further suggests that thermal nitridation moves the oxide traps farther away from the Si-SiO/sub 2/ interface and thus suppresses the Coulombic scattering of mobile electrons by the trapped charges. Both nitridation-induced interfacial modifications result in enhanced high-field mobility of nitrided-oxide devices over the standard MOS devices. >
IEEE Electron Device Letters | 1992
Z.H. Liu; P. Nee; Ping Keung Ko; Chenming Hu; Charles G. Sodini; B.J. Gross; T. P. Ma; Y.C. Cheng
The effects of injection current density and temperature on time-dependent dielectric breakdown (TDDB) of low-pressure thermally reoxidized-nitrided oxides (RNOs) and fluorinated oxides (FOs) with equivalent oxide thicknesses of 100 AA were examined. Time to breakdown for RNO was found to be improved over that for thermal oxide while both the impact ionization coefficient and the activation energy of lifetime are comparable to those of control oxide. On the other hand, no obvious TDDB improvement was observed for FO. This observation, in conjunction with the results for charge trapping measurements at different temperatures, indicates that the lifetime improvement for RNOs might be due to the reduced charge traps in these films. I-V ramp tests have shown that RNO has a comparable density to that of control oxide.<<ETX>>
IEEE Transactions on Electron Devices | 1994
Zhi-Jian Ma; Zhihong Liu; J. T. Krick; H. J. Huang; Y.C. Cheng; Chenming Hu; Ping Keung Ko
This paper presents a study of the impact of gate-oxide N/sub 2/O anneal on CMOSFETs characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 /spl Aring/) and five N/sub 2/O anneal conditions (900/spl sim/950/spl deg/C, 5/spl sim/40 min) plus nonnitrided process and channel lengths from 0.2 to 2 /spl mu/m were studied to establish the correlation between the nitrogen concentration at Si/SiO/sub 2/ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N/sub 2/O anneal step can increase CMOSFETs lifetime by 4/spl sim/10 times, effectively suppress boron penetration from the P/sup +/ poly-Si gate of P-MOSFETs without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO/sub 2/ interface. The optimal N/sub 2/O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO/sub 2/ interface which can be realized by annealing 60/spl sim/110 /spl Aring/ oxides at 950/spl deg/C for 5 min or 900/spl deg/C for 20 min. >
IEEE Transactions on Electron Devices | 1989
K.K. Hung; P.K. Ko; C. Hu; Y.C. Cheng
A computer-controlled system for measuring the random telegraph noise in small-area MOSFETs is described. The key element is a specially designed current amplifier that employs a feedback technique to separate the fluctuating and DC parts of the drain current. Techniques for automatic extraction of the fluctuation amplitude and time constants from the raw data are also discussed. >
IEEE Transactions on Electron Devices | 1993
Z.J. Ma; P. T. Lai; Y.C. Cheng
The significant off-stage gate current of nitrided-oxide n-MOSFETs can be attributed to severe hot-hole injection into the gate oxide during band-to-band (B-B) tunneling due to a nitridation-induced lowering of the barrier height for hole injection. Some of the injected holes are even trapped in the gate oxide above the deep-depletion layer of the drain and thus decrease the gate-induced drain leakage (GIDL) current. A subsequent hot-electron injection into the gate oxide can neutralize these trapped holes and make the reduced GIDL current recover, even increase beyond the original value. The proposed mechanism of the GIDL degradation and recovery behaviors can be confirmed by the observed change in the ratio of the substrate to source currents, as well as by the field-distribution analysis of the gate oxide under stressing. >