Y.D. Chan

Impact of polysilicon dry etching on 0.5 /spl mu/m NMOS transistor performance: the presence of both plasma bombardment damage and plasma charging damage

Two types of damage mechanisms resulting from polysilicon gate dry etching are identified in 0.5 /spl mu/m NMOS transistors. One type of damage is found to be active even after full processing and to result in positive charge at the edge of the gate oxide. It is found to have no correlation with polysilicon antenna ratio and to be attributable to direct plasma bombardment. The other type of damage is found to be passivated after full processing but it is activated by electrical stress. After activation, this damage is an increasing function of polysilicon antenna ratio as well as overetch percentage. This second type of damage is attributable to plasma charging.<<ETX>>

Electrical properties of contact etched p‐Si: A comparison between magnetically enhanced and conventional reactive ion etching

We report the results of a comparative study of the damage induced in boron‐doped Si by contact etching. The two approaches compared are conventional reactive ion etching and magnetically enhanced reactive ion etching (MERIE). The two structure‐chemistry combinations used are SiO2/Si with CHF3/O2 plasmas, and bare Si wafers with CHF3/Ar plasmas. The damage examined in the Si substrates of both structures is that of electronic states in the band gap, the permeation into Si of hydrogen, and the deactivation of boron acceptors. These types of damage are explored by means of deep level transient spectroscopy and capacitance‐voltage measurements on Ti/Si Schottky diodes fabricated on the etched substrate surfaces. The gap states induced by these contact etches are ascribed to interstitial‐atom‐related defects which are proposed to be formed as a result of interactions involving self interstitials. During etching these defects are observed to be both generated by the etching process itself as well as electrical...

Degradation of submicron N-channel MOSFET hot electron reliability due to edge damage from polysilicon gate plasma etching

The impact of poly-Si gate plasma etching on the hot electron reliability of submicron NMOS transistors has been explored. The results show that the gate oxide and SiO/sub 2/-Si interface near the drain junction have a susceptibility to hot electron injection that increases with overetch time. We show for the first time that this degradation of hot electron reliability is attributable to the edge type of gate oxide damage resulting from direct plasma exposure during overetch processing. We demonstrate that this type of damage does not scale with channel length and becomes even more important in shorter channel transistors.<<ETX>>

Electronic states created in p‐Si subjected to plasma etching: The role of inherent impurities, point defects, and hydrogen

Reactive ion etching and magnetically enhanced reactive ion etching with CHF3/O2 are employed to remove SiO2 from boron‐doped Si substrates. Etch‐induced gap states in the substrate are monitored using deep‐level transient spectroscopy. The dominant state is found to be a donor with a hole binding energy of 0.36 eV. The state has been identified as that of the carbon‐interstitial oxygen‐interstitial pair. The depth profile of the pair is determined by two competing mechanisms: the pair generation and its electrical deactivation by atomic hydrogen. The latter process is especially prevalent in the presence of a magnetic field.

Observation of a new type of plasma etching damage: Damage to N‐channel transistors arising from inductive metal loops

We report a new type of damage, referred to here as inductive damage, induced by metal 1 plasma etching. The devices used in this study are lightly doped drain n‐channel metal–oxide semiconductor field effect transistors (MOSFETs) fabricated on 200 mm p/p+ silicon wafers. The channel lengths of the investigated transistors are 0.5 μm with 90 A thick thermally grown gate oxides. The metal 1 main etch (duration 30 s) and overetch (50%) employed BCl3/N2/Cl2 chemistry and was done using a standard reactive ion etching tool operated at rf power of 600 W and rf frequency of 13.56 MHz. Specially designed MOSFETs with inductive metal loops connecting the gate and substrate or the gate and drain are used to examine inductive damage. Inductive damage is shown to arise from electrical stress of the gate oxide and oxide/Si interface by the electromotive force generated in the metal loops by the metal plasma etch.

Soft-breakdown damage in MOSFET's due to high-density plasma etching exposure

Gate leakage current densities on the order of nA//spl mu/m/sup 2/ at operating voltage levels have been observed in MOSFETs that were processed in a high-density plasma (HDP) oxide etch tool, yet these transistors have performance parameters that are within 10% of controls. These high gate leakage currents seen in the HDP etched devices were not observed in controls. Direct observation shows that these HDP exposed devices have light emission at higher voltages in the region where the gate poly-Si crosses the birds beak. Light emission in this region is also not observed in controls.

Electrical characterization of the Si substrate in magnetically enhanced or conventional reactive-ion-etch-exposed SiO/sub 2//p-Si structures

The authors explore the silicon substrate damage produced by Cl/sub 2/- and HBr-based reactive ion polycrystalline silicon overetches used in the definition of polycrystalline-Si/SiO/sub 2//single-crystal-Si structures. The damage-caused traps, examined by means of deep-level transient spectroscopy, in the p-type Si are found to have concentrations that can exceed one tenth that of the boron dopant, and are detectable as far as approximately 10 mu m from the SiO/sub 2//Si interface. The concentration and depth of these traps are shown to depend on the polycrystalline Si overetch selectivity, on the initial oxide thickness, and on the magnetic field strength, as well as on the presence of hydrogen.<<ETX>>

Detection and comparison of localized states produced in poly‐Si/ultra‐thin oxide/silicon, structures by plasma exposure or plasma charging during reactive ion etching

An approach using two terminal current measurements obtained in a cyclic current–voltage sweeping procedure, is shown to be very useful in detecting damage in poly‐Si/ultra‐thin SiO2/substrate Si gate structures subjected to dry etching. The current peaks seen in this approach, are shown to be due to displacement currents and to have different features depending on whether the capacitor structures were subjected to plasma charging currents, or plasma photon/particle exposure during etching. A model is presented relating these features to localized states at or near the SiO2/substrate interface.

Cyclic current-voltage characterization applied to edge damage evaluation in gate definition plasma etching

A simple two-terminal cyclic current-voltage (I-V) measuring approach is used to monitor damage in gate definition plasma etching of poly-Si gate 70 /spl Aring/ oxide MOS structures. This new technique is used to identify the presence of trapping and near-surface silicon substrate generation lifetime changes due to edge exposure.

Observation of Electrolurninescence and "Soft-breakdown" Effects in Sub-0.5/spl mu/m CMOS with Ultrathin Gate Oxides

Lurmnescence from reverse biased pn junctions and gate regions of MOSFETs is well known[l3]. However, there are four new aspects to the light emission observed in this study from the MOSFET gate areas : (1) the devices used were sub half micron geometry NMOS and PMOS transistors with oxide thicknesses in the range of 45 to 135% (2) light emission is observed at the poly gate-birds beak edge, (3) only devices that had antennas designed for the contact etch step and were processed in a high density plasma etch system exhibit this luminescence, and (4) the presence of nondestructive luminescence correlates with the presence of oxide “soft-breakdown”. The transistors used in this study were LDD CMOS fabricated on 8 in. epi wafers. Gate oxide thicknesses were in the range of 45A to 135w and channel lengths were from 0 . 3 5 ~ to 0.6p.m. Devices with antennas (to intensie the effects of certain plasma processing steps) and control devices (without antennas) were also fabricated. Contact etch antennas consisted of increasing numbers of contacts between metal and poly pads. Our investigations found that biasing conditions for these transistors that put the substrate surfkce into inversion and could lead to impact ionization and subsequent recombination were needed to stimulate and maintain nondestructive light emission from the gate area. For example , the source and drain of transistors had to be floating while the gate was biased to invert the substrate with a large voltage (Vg>lSV). Other biasing conditions, e.g. source and drain grounded, were observed to cause poly gate “ bum-out” . We found that this nondestructive electroluminescence occurred only in devices that had antennas for the contact etch and that these same transistors had a current-voltage behavior we term ‘-soft breakdown. Fig.la shows pictures of light mussion from the gate region (over the birds beak area) that was biased into light emission for several hours by having the source/drain float, whereas Fig.lb shows the poly burning out over the field oxide which was biased with the source/drain grounded. Both pictures were taken using a laser scanning microscope. Fig.2 shows a typical gate leakage current density (Jg) dependence on gate voltage (Vg) in transistors that exhibit the nondestructive gate luminescence. As can be seen in Fig.2, Jg in these transistors is very large (-nA/pm2 at 3.3V). This is in contrast to Jg<lpA/pn2 for control devices. A cumulative plot of the gate leakage current at g . 3 V in luminescent transistors with 9OA thick gate oxides is given in Fig.3. It can be seen from Fig.3 that Jg is very much dependent on antenna ratio with values of the order of 111Np.m~ which tend to be larger for PMOS devices. This trend is also seen in all luminescent transistors with other gate oxide thicknesses. These luminescent transistors with their large Jg values display a “soft-breakdown”; i.e., ail other transistor parameters, namely threshold voltage (Vth), transconductance (gm) and sub-threshold slope (S), are within 10% of those of control transistors, inspite of their high leakage currents (Fig.4). Also the luminescent transistors maintain their transistor characteristics after the application of Fowler-Nordheim stress with a constant current in the -100p~/pn* for significantly long durations. All this takes place with no change in Vth, gm or S. This electroluminescence and soft-breakdown are explained in terms of a model that assumes the generation of localized leakage paths induced in the gate oxide by the contact etching (plasma) process.