Y.L. Le Coz

A stochastic algorithm for high speed capacitance extraction in integrated circuits

Abstract We present the theory of a novel stochastic algorithm for high-speed capacitance extraction in complex integrated circuits. The algorithm is most closely related to a statistical procedure for solving Laplaces equation known as the floating random-walk method. Overall computational efficiency stems from various factors: suitability to rectilinear geometries, statistical-error cancellation, selective integration over Gaussian surfaces and direct capacitance-matrix evaluation. Our analysis begins with Laplaces equation for a scalable square domain, subject to arbitrary Dirichlet conditions. A boundary-integral solution is then found, from which are obtained integrals for electric potential and electric field at the domain center. An electrode-capacitance integral is next derived. This integral is expanded as an infinite sum, and probability rules that statistically evaluate the sum are deduced. These rules define the algorithm. Three sources of numerical error associated with the algorithm have been identified. They are series-truncation error, space-discretization error and statistical error. All these errors can be adequately controlled through proper adjustment of algorithm parameters.

Performance of random-walk capacitance extractors for IC interconnects: A numerical study

Abstract With ever-shrinking feature geometries, multilevel IC interconnects will greatly influence overall circuit behavior. In particular, efficient numerical evaluation of 3D IC-interconnect capacitance is essential to achieving targeted design goals. Previously, we have reported a new random-walk (RW) algorithm for extracting capacitance of complex multilevel IC interconnects [see, Y.L. Le Coz and R.B. Iverson, Solid-St. Electron. 35, 1005 (1991)]. Here, for the first time, we present a numerical study concerning the influence of interconnect complexity on RW-extractor performance. Of primary interest, are the empirical relationships among geometric complexity, run time, and memory usage. We also include, for reference, comparisons with conventional finite-element (FE) and boundary-element (BI) capacitance extractors. Despite the general computational limitations of these conventional extractors, we have attempted to normalize numerical errors to a single common value. The problem geometry selected for our study consists of a long “bus” wire situated beneath a series of shorter cross wires. Problem complexity is controlled by increasing the bus-wire length and adding cross wires. We have found that at 1% normalized error in bus-wire self-capacitance, the RW extractor has the shortest execution time, which is uniquely independent of problem complexity. In addition, because the RW extractor requires no numerical meshing, an RW:BI:FE memory-usage ratio of 1:103:107 was observed. We conclude that the RW method may possibly excel in the high-complexity regime characteristic of multilevel IC interconnects.

An improved floating-random-walk algorithm for solving the multi-dielectric Dirichlet problem

An improved floating-random-walk algorithm for solving the multidielectric Dirichlet problem is outlined. The improvement is achieved by using statistically generated Greens functions that are calculated beforehand and stored as lookup tables. These tables have been used to solve the multidielectric Dirichlet problem for an arbitrary two-dimensional geometry. The improved algorithm is also compared with the conventional floating-random-walk algorithm and is found to be at least two times more efficient. Results are presented for two types of parallel-plate geometries. >

A high-speed capacitance extraction algorithm for multi-level VLSI interconnects

The authors present preliminary results of a novel stochastic algorithm for high-speed capacitance extraction in multi-level VLSI interconnects. The algorithm is related to a statistical procedure for solving Laplaces equation known as a floating random-walk method. Benchmark calculations for three-dimensional cross-wire geometries were performed on a MAC IIfx personal computer, operating at 0.3 MFLOPS. Execution times were typically 40 s for an accuracy of less that 5%. Overall computational efficiency stems from various factors: suitability to rectilinear geometries, statistical-error cancellation, selective integration over Gaussian surfaces, and direct capacitance-matrix evaluation.<<ETX>>

A high-speed multi-dielectric capacitance-extraction algorithm for MCM interconnects

The authors report an extension of a stochastic algorithm for capacitance extraction in complex two- and three-dimensional multidielectric structures. The algorithm has applications in the area of circuit modeling of multichip modules. The extension is in the form of a simple probability rule that depends on the ratio of electric permittivities across dielectric interfaces. Computational results are presented for a two-dimensional cross-section of a wire running over a dielectric and ground plane. Results are also presented for a three-dimensional interconnect via partially embedded in a dielectric over a ground plane. All computations were performed on a personal computer. Execution times were nominally five minutes for statistical errors ranging from one to ten percent, depending on dimensionality and value of the dielectric constant. An extraction methodology was devised for large conductor arrays based on superimposing a geometrical hashing grid.<<ETX>>

Ehrenfest derivation of forces acting within semiconductors of inhomogeneous material composition

Abstract An Ehrenfest derivation for the forces within semiconductors of inhomogeneous material composition is provided. An illustrative 1-D analysis, under the extended Wannier-Slater approximation, is presented. Only two types of force are found to exist: one from charges constituting the semiconductor lattice, and the other from global inhomogeneities in free-carrier and ionized-impurity charge throughout the semiconductor. The so-called “entropy force” does not arise from our Ehrenfest analysis.

A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines

We have created a stochastic impulse-response (IR) moment-extractionalgorithm for RC circuit networks. It employs anewly discovered Feynman Sum-over-Paths Postulate. Fullparallelism has been preserved. Numerical verification resultsfor coupled RC lines confirmed rapid convergence. We believethis algorithm may find useful application in massively coupledelectrical systems, such as those encountered in high-enddigital-IC interconnects.

An equilibrium model of the semiconductor heterojunction diode based on kinetic theory

A mathematical model for a semiconductor heterojunction diode at equilibrium based on kinetic theory of inhomogeneous systems is presented. A generalized Boltzmann equation for variable effective mass is obtained from Marshak and van Vliet’s extended Wannier–Slater Hamiltonian [Solid‐State Electron. 21, 417 (1978)]. An Ehrenfest correspondence procedure has shown that only forces due to variation in band‐edge energy and electric potential energy arise; the supposed force arising from the spatial gradient of effective mass does not exist. The diode model consists of three separate regions: two regions of homogeneous material composition and a finite interface region of inhomogeneous composition. Boltzmann’s equation is solved in each region as a function of arbitrary electric potential. Physically reasonable boundary and continuity conditions are also established. Closed‐form analytical solution of our model equations does not appear to be possible because of the coupling with Poisson’s equation. To demons...

An analytical model for a.c. transport in double-barrier heterojunction diodes

Abstract We propose an analytical model for small-signal a.c. transport in double-barrier heterojunction diodes (DBDs). The model relies on the transfer-Hamiltonian method as modified for systems with harmonic tunneling potentials. Band structure, double-barrier geometry, and position of quasi-Fermi energies incorporate directly into the model. Salient features of the DBD frequency response arise from a frequency-dependent integration kernel, in the form of an overlap matrix element. A new prediction of the model is finite response beyond the quasi-static limit Δϵ h (where Δϵ is the resonance energy width) due to transitions between quasi-bound states.

Iterative Spectral Solution of Boltzmann’s Equation for Semiconductor Devices

An iterative spectral method for solving Boltzmann’s equation is formulated. It is used to analyze collisionless transport in a one-dimensional silicon device structure. The obtained distribution functions are compared with exact analytical solutions. It is found that the spectral method is a highly efficient alternative to Monte Carlo.