Yandong He

Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO/sub 2/ gate stack with low preexisting traps

In this letter, the positive-bias temperature instability (PBTI) characteristics of a TaN/HfN/HfO/sub 2/ gate stack with an equivalent oxide thickness (EOT) of 0.95 nm and low preexisting traps are studied. The negligible PBTI at room temperature, the so-called turn-around phenomenon, and the negative shifts of the threshold voltage (V/sub t/) are observed. A modified reaction-diffusion (R-D) model, which is based on the electric stress induced defect generation (ESIDG) mechanism, is proposed to explain the above-mentioned PBTI characteristics. In this modified R-D model, PBTI is attributed to the electron-induced breaking of Si-O bonds at interfacial layer (IL) between HfO/sub 2/ and Si substrate and the diffusion/drift of oxygen ions (O/sup -/) from Si-O bonds into HfO/sub 2/ layer under positive-bias temperature stressing. The ESIDG mechanism is responsible for the breaking of Si-O bonds. The measured activation energy (E/sub a/) is consistent with the one predicted by the ESIDG mechanism.

New Observations on the Hot Carrier and NBTI Reliability of Silicon Nanowire Transistors

Hot carrier injection (HCI) and negative bias temperature instability (NBTI) reliability of n-channel and p-channel silicon nanowire transistors (SNWTs) have been investigated in this paper. It was found that the worst-case bias for HCI in n-type SNWTs is different from the conventional planar devices, and HCI is not a critical concern for ultra-scaled SNWTs. For the pMOSFETs, NBTI in SNWTs is relatively severe and exhibits new characteristics. Fast degradation and quick saturation of NBTI were observed due to the structural nature of nanowire devices. AC NBTI of SNWTs was found to be frequency independent. Different recovery behaviors of NBTI in SNWTs under positive and negative/zero bias were observed and discussed. The NBTI-induced additional fluctuation on device degradation of short-channel SNWTs was observed and studied.

Multiregion DCIV: A Sensitive Tool for Characterizing the

By measuring the substrate current under the forward bias of source/drain-substrate junction, a multiregion direct current current-voltage (MR-DCIV) technique is used to characterize the interface trap density and location in shallow-trench-isolation (STI)-based laterally diffused metal-oxide-semiconductor devices. The interface traps in LDMOSFETs yielded sharp well-resolved peaks in MR-DCIV current spectra. The interface traps in STI region can be measured without inducing any potential damages on the gate oxide by this nondestructive characterization tool. This technique can provide not only across-wafer as-grown interface trap profile but also stress-induced defect information.

\hbox{Si/SiO}_{2}

Multilevel cell storage allows two or more bits to be stored in one cell, thus reducing almost 50% of Flash memorys area without technology shrinkage. Basic concepts like sensing schemes in multilevel Flash memory are fundamental and need further research. In this paper, an innovative sensing architecture is presented, with the name of serial-parallel sensing scheme, which provides fast read speed and a medium area cost and power consumption, compared with conventional parallel and serial sensing schemes. Using 65nm technology, the new architecture performs well, almost five times as fast as serial sensing and has advantage over parallel sensing in both area and power consumption cost.

Interfaces in LDMOSFETs

In this letter, negative bias temperature instability (NBTI) in silicon nanowire field-effect transistors (SNWFETs) is investigated and found to exhibit some new characteristics that are probably due to the structural nature of nanowires. In long-channel SNWFETs, a fast degradation and a quick saturation of NBTI are observed and discussed. In short-channel SNWFETs, a large fluctuation of NBTI is observed, which mainly originates from the ultrasmall gate areas of the short-channel SNWFETs and the statistical nature of randomly trapped charges in the oxide and at the Si/SiO2 interface. Techniques to suppress the fluctuation and characterize the intrinsic NBTI in ultrasmall SNWFETs are proposed and discussed. A recently developed online gate current method is demonstrated, which effectively alleviates this NBTI fluctuation in SNWFETs.

An innovative sensing architecture for multilevel Flash memory

The STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process. In this paper, a multi-region trap characterization direct current current-voltage (MR-DCIV) technique was proposed to characterize interface state generation in both channel and STI drift regions. The correlation between interface trap and MR-DCIV current has been verified by two-dimensional device simulation. Degradation of STI-based LDMOS transistors in various reliability stress modes is investigated experimentally by proposed technique. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our study reveals that OFF-state stress becomes the worst degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.

Characteristics and Fluctuation of Negative Bias Temperature Instability in Si Nanowire Field-Effect Transistors

The paper introduces a new monitoring circuit to quantify the change in performance of devices undergoing NBTI stress at 65nm technology node. The proposed solution consists of a pMOS device experiencing accelerated NBTI stress, a Capacitive Switch, Relaxation Oscillator structure, serving as a monitoring unit, which allows to dynamically track the NBTI-induced degradation with time. The circuit measures the change of the relaxation frequency which is attributed to the saturation current shift in pMOSFET due to NBTI stress. The proposed circuit with counting unit produces a digital output which makes it easier to collect. The capacitive relaxation oscillator modeling has been established and verified by the experiments. Meanwhile, the circuit is easily to be integrated with the digital logic system. Based on the device matrix, the effect of initial saturation current distribution and NBTI-induced time-dependent variability can also be obtained.

A multi-region trap characterization method and its reliability application on STI-based high-voltage LDMOSFETs

1.Introduction With IC industry improving and device scaling, reliability is becoming more serious. The Negative Bias Temperature Instability (NBTI) is a main degradation mechanism in p-MOSFET devices. Under negative voltage bias and elevated temperature, more interface traps generate and cause the threshold voltage shift [2]. When the threshold voltage shifts, drain current and transconductance for p-MOSFETs reduce, which are considered as major reliability issues in digital and analog IC. Such degradation shortens the device lifetime, and even influences the whole integrated circuits. At the same time, device scaling means more MOSFET devices on a chip. The critical parameters play an important role in the time-based reliability [3]. Therefore it is necessary to test and analyze the threshold voltage mismatch before MOSFET devices are put into use. Some VT extractor realizations have been published [4-7]. An array-based structure for measuring the electrical property of large numbers of MOSFETs is also proposed in [8]. In this paper, we report a simple circuit for the measurement of threshold voltage shift and fluctuation, which can monitor the NBTI degradation directly and effectively. The characteristics of the circuit and the simulation results are then discussed.