Yao-Hong Liu

Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-

This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma (¿¿) fractional-N PLL. The proposed CP circuit achieves good up/down current matching, while the proposed linearization method enables the PFD/CP system to operate at an improved linear region. The proposed techniques are demonstrated in the design of a 2.4-GHz ¿¿ fractional-N PLL. The experimental results show these techniques considerably improve the in-band phase noise and fractional spurs. In addition, the proposed gated-offset CP topology further lowers the reference spurs by more than 8 dB over the conventional fixed-offset approach. This chip is implemented in the TSMC 0.18-¿m CMOS process. The fully-integrated ¿¿ fractional-N PLL dissipates 22 mW from a 1.8-V supply voltage.

N

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed sigma-delta modulated phase rotator (¿¿-PR). By properly combining the multi-phase signals from the PLL output, the ¿¿-PR effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed ¿¿-PR adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the ¿¿-PR on the TX output noise is also analyzed in this paper. The proposed TX with the ¿¿-PR is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 ¿m CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of -11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.

PLLs

This paper presents a 400-MHz energy-efficient offset quadrature phase-shift keying (O-QPSK) transmitter for implantable multichannel neural recording applications. Transmitters for these applications must operate at low power while delivering a high data rate. The proposed transmitter incorporates a phase MUX, which directly implements the phase-shift keying operation. The O-QPSK modulation signal is generated by selecting one of the four quadrature phases based on the baseband data via the phase MUX. The power amplifier adopts the inverter-type topology for it is compatible with the quasi-constant-envelope nature of the O-QPSK signal. Implemented in a 0.18- mum CMOS process, the whole transmitter dissipates 2.9 mA from a 1.2-V supply. With a maximum data rate of 17.5 Mb/s, the proposed transmitter achieves an energy efficiency of 200 pJ/bit and is capable of delivering an output power up to -8 dBm.

A Wideband PLL-Based G/FSK Transmitter in 0.18

This paper reports a PFD/CP linearization technique and a new charge pump circuit to enhance the performance of a delta-sigma (DeltaSigma) fractional-N PLL. The proposed method improves the PLL linearity by forcing the PFD/CP to operate in a linear part of its transfer characteristic; while the CP circuit minimizes the current mismatch between the up and down currents by feedback. These circuit techniques are employed in the design of a 2.4-GHz DeltaSigma fractional-N PLL. This chip has been fabricated in the TSMC 0.18-mum CMOS process. The experimental results demonstrate that the proposed techniques considerably improve the fractional-N PLL performance. This fully-integrated PLL dissipate 22 mW under a 1.8-V supply.

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A low-power super-regenerative receiver (SR-RX) with a digitally-controlled oscillator for the capsule endoscope system is reported in this paper. In this work, an open-loop frequency calibration loop is proposed to adjust the oscillator center frequency to the desired frequency band. The RX operates in the 402-405 MHz MICS band, and is designed to receive on-off keying modulation signal. This chip was fabricated in the TSMC 0.18-mum CMOS process. The RX start-up time is only 14.8 mus and is capable of a maximum data rate of 1 Mbps. The SR-RX consumes 5.5 mW from a 1.5-V supply voltage.

m CMOS

A 400-MHz phase-mux-based O-QPSK transmitter (TX) for medical imaging applications is presented in this paper. The modulation signal is generated by selecting one of the four quadrature phases to the TX output via a proposed Phase MUX. An inverter-type power amplifier is utilized for it is compatible with the quasi constant-envelope nature of the O-QPSK modulation. Fabricated in a 0.18-mum CMOS process, the whole TX draws 2.9 mA from a 1.2-V supply. With a maximum 15-Mbps data rate, the TX achieves an energy efficiency of 0.23 nJ/bit and delivers an output power up to -7 dBm.

A 200-pJ/b MUX-Based RF Transmitter for Implantable Multichannel Neural Recording

This paper presents a delta-sigma pulse-width digitizer (ΔΣ-PWD) architecture designed for a super-regenerative receiver (SR-RX) operated at the 400-MHz Medical Implantable Communications Service (MICS) band. The ΔΣ-PWD employs the operation principle of a ΔΣ modulator to convert the pulse-width (PW) value into digital domain and achieve fine resolution, which allows the SR-RX to support the 2-ASK/4-ASK modulations. It can be considered as the PW domain counterpart of a conventional ΔΣ modulator. The proposed architecture is capable of suppressing the PW quantization error over the direct-sampling-type PW detector by 23 dB. A linear model for the ΔΣ-PWD is devised in this paper for system analysis and design optimization. Fabricated in a 0.18-μm CMOS process, the whole receiver draws 700 μA from a 1.3-V supply, while the ΔΣ-PWD consumes only 100 μA. When operated on the 4-ASK modulation signal with 312-kbps data rate, the receiver achieves an energy efficiency of 2.9 nj/bit and -76-dBm sensitivity.

A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit

An asymmetrical wireless interface and transceiver designed for implanted medical image applications are reported. The proposed system operated at the 402-405 MHz MICS (medical implantable communication system) band, and it utilizes different modulation schemes for uplink and downlink to lower power consumption and reduce circuit implementation complexity. A high data rate (524 kbps within 300-kHz channel and maximum 1.5 Mbps) and low-power (12.7 mW) direct-modulation FSK transmitter is proposed for medical image transmission, and a low-power (3.3 mW) superregenerative OOK receiver is adopted for command receiving. The wireless interface design considerations and key circuit realizations are presented in this paper.

A 400-MHz super-regenerative receiver with digital calibration for capsule endoscope systems in 0.18-μm CMOS

This paper presents a 400-MHz energy-efficient Medical Micro-power Networks transmitter for neural-muscular signal sensing and stimulation applications. The transmitter can fulfill the transmission requirements defined in the MedRadio band, including the recently added 413-MHz to 457-MHz channels. The half-sine shaped offset-QPSK modulation is adopted to meet the transmission mask requirement while supporting a maximum data rate of 4 Mbps within the 6-MHz channel bandwidth. The signal modulation is performed by the proposed FIR-embedded phase modulator which employs a phase-domain FIR filter to suppress the unwanted side-lobe energy. Fabricated in a 0.18-μm CMOS process, the presented transmitter consumes only 2.6 mW from a 1-V supply, resulting in an energy efficiency of 650 pJ/bit. The measured error vector magnitude is 2.5%.

A 3.5-mW 15-Mbps O-QPSK transmitter for real-time wireless medical imaging applications

An energy-efficient PLL-based FSK transmitter is reported in this work. The PLL output signal is manipulated by a sigma-delta modulated phase rotator, whose output frequency is controlled by the input data, to produce FSK signals. Since the data is applied outside the PLL, the frequency modulation characteristics are no longer constrained by the PLL loop. Fabricated in a 0.18-mum CMOS process, the whole transmitter draws 13 mA from a 1.5-V supply. With a 1.5-Mbps data rate, the transmitter achieves an energy efficiency of 13 nJ/bit, and delivers an output power of -9 dBm.