Chang-Tsung Fu

Low-Noise Amplifier Design With Dual Reactive Feedback for Broadband Simultaneous Noise and Impedance Matching

The simultaneous noise and impedance matching (SNIM) condition for a common-source amplifier is analyzed. Transistor noise parameters are derived based on the more complete hybrid-¿ model, and the dominant factors jeopardizing SNIM are identified. Strategies for narrowband and broadband SNIM (BSNIM) are derived accordingly. A dual reactive feedback circuit along with an LC-ladder matching network is proposed to achieve the BSNIM. It includes a capacitive and an inductive feedback, where the former utilizes the transistor parasitic gate-to-drain capacitance and the latter is formed by transformer coupling. This circuit topology has been validated in 0.18- and 0.13- ¿m CMOS technologies for a 3-11-GHz ultra-wideband (UWB) and a 2.4-5.4-GHz multistandard application, respectively. The 3-11-GHz UWB low-noise amplifier is detailed as a design example.

A 2.4–5.4-GHz Wide Tuning-Range CMOS Reconfigurable Low-Noise Amplifier

A 2.4-5.4-GHz CMOS reconfigurable low-noise amplifier (LNA) is designed. It consists of two stages: a broadband input stage for a steady input matching and noise performance, and a reconfigurable band-selective stage which provides a wide-range frequency tuning from 2.4 to 5.4 GHz and a 12-dB stepped gain with linearity adjustment. The frequency tuning is conducted by a multitapped switching inductor and varactors. Careful design of the switching inductor achieves consistent performance among frequency configurations. The stepped gain and linearity adjustment are provided by a size-switchable transistor with a variable biasing. Fabricated in 0.13 mum CMOS technology this LNA exhibits performance including up to 25 dB power gain, 2.2-3.1 dB noise figure and less than 5 mW power consumption under 1 V power supply.

A 2.4 to 5.4 GHz Low Power CMOS Reconfigurable LNA for Multistandard Wireless Receiver

A CMOS reconfigurable LNA is reported. By combination of switched inductors and varactors it performs continuous frequency tuning from 2.4 to 5.4 GHz with 500 MHz 3 dB-bandwidth. Switching transistor is used to provide variable gain control over a 12 dB-range. The LNA supports standards including Bluetooth, WiMAX, UWB mode-1, 802.11 b/g and part of 802.11a. Fabricated in 0.13 um CMOS process the LNA achieves up to 25 dB power gain, 2.2 dB noise figure, -1 dBm IIP3 while consuming less than 5 mW from 1-V power supply.

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

An × 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.

Wide-Band Inductorless Low-Noise Transconductance Amplifiers With High Large-Signal Linearity

Two high-linearity inductorless broadband low-noise transconductance amplifiers (LNTAs) employing noise and distortion cancellation techniques are presented. The core design employs a common-gate input stage and a common-source error-amplifier (EA) stage. Stacked PMOS-NMOS topology enables large-signal operation while the drain current is reused. The high linearity performance is achieved by the derivative superposition of the pMOS and nMOS transistors that reduce the third-order distortion due to second-order interaction between input stage and EA stage. Critical design issues are carefully investigated along with the performance tradeoffs. In the fully differential architecture, the first LNTA covers 0.1-2-GHz bandwidth and achieves a minimum noise figure (NF) of 3 dB, third-order input intercept point (IIP3) of 10 dBm, and a 1-dB compression point of 0 dBm while dissipating 30.2 mW of dc power. The second lower power LNTA with bulk-driven technique achieves a minimum NF of 3.4 dB, IIP3 of 11 dBm, 0.1-3-GHz bandwidth at 16 mW of power consumption. Each LNTA occupies an active area of 0.06 mm2 in 45-nm CMOS.

A 2.5GHz 32nm 0.35mm 2 3.5dB NF −5dBm P 1dB fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection

Process scaling enables SoC integration of radio and large digital systems at reduced cost and area. Furthermore, the crowded spectrum requires high linearity receivers to enable co-existence in the 2.4GHz ISM band. Inductorless LNA designs have been studied to make use of the excess fT in advanced CMOS technologies to lower cost [1]. However, an inductively tuned LNA has the advantage of improved out-of-band rejection, and can be readily integrated with a transmit/receive (T/R) switch to provide isolation in the TX mode without the need for additional inductors [2]. In this paper, a 2.5GHz fully differential tuned LNA with integrated T/R switch is designed in a High-K metal gate 32nm digital CMOS process, and packaged in an SoC-compatible flip-chip package. Reliability constraints of the package severely limit the ability to depopulate soldering bumps, and RF components must be designed taking the bump location into account. The LNA achieves a 3.5dB NF, −5dBm P1dB at 2.5GHz while drawing 11mA from a 1.8V supply. LNA performance is enabled by (1) use of a push-pull topology that exploits the equal strength of p and n transistors to improve linearity, (2) use of nested coupled inductors (NCI) for low-noise input matching and to reduce area. The T/R switch handles 34dBm of power with an insertion loss of 1.1dB at 2.5GHz. T/R switch performance is enabled by (1) reuse of LNA gate inductor to enable low RX mode loss [2], (2) use of remote body-contacted TX switch with high power handling and ESD protection for a transformer-coupled PA.

A 5-GHz, 30-dBm, 0.9-dB insertion loss single-pole double-throw T/R switch in 90nm CMOS

A 5 GHz, 30-dBm CMOS T/R switch implemented in 90 nm CMOS is reported. A body isolation technique is employed and optimized for power handling capability. Inductors are employed with the transistor switches for parallel resonance to improve isolation. Thick oxide NMOS transistors are used for the switching transistors and placed inside the inductors to reduce the active chip area to approximately 0.2 mm2. 0.9-dB insertion loss for both TX and RX modes is achieved with a 5-V control voltage.

32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver

Embedded PC applications are growing, driven by their cost, performance and software compatibility. The SoC described in this work is a unique device designed for rapid integration and customization for specific market segments. A rich multi-source IP eco-system consisting of standardized interfaces, modular and configurable building blocks, enables automation and fast execution to deliver a broad range of targeted solutions. Integrating high-performance digital circuits with analog and RF circuits on a leading edge process enables our SoC architecture to increase the level of integration, performance and reduce the cost of the platform. WiFi has remained an external PC component due to the challenges of managing system noise from the digital circuits. This paper presents an integrated standard x86 OS compliant, dual-core ATOM® processor-based SoC, including the RF WiFi to drive down platform cost. Key enabling features are: (a) a 32nm RF process with HV transistors and RF passives; (b) an on-chip interconnect fabric for modularity; (c) a clock generator with SSC to reduce substrate noise injection and EMI; (d) voltage regulators for power management and rail reduction; (e) an 802.11b/g RF WiFi transceiver with integrated LNA, PA, T/R switch and BIST/calibration engine.

(Invited) An Ultra-Low Insertion Loss T/R switch fully integrated with 802.11b/g/n transceiver in 90nm CMOS

An Ultra Low Insertion loss T/R switch fully integrated with 802.11 b/g/n direct conversion transceiver front end in 90 nm CMOS. The receiver achieves 3.6 dB NF at 2.4 GHz. The T/R switch has been designed and tested and has 0.3 dB insertion loss in the transmit mode and adds 0.1 dB of NF in the receive mode while occupying 0.02 mm2 of the die area.

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS

A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization the TX delivers 19.8dBm at 12.5% efficiency (PA 21.6dBm/19.7% PAE) for -25dB EVM and mask-compliant 22.8dBm/18.5%, while the RX achieves 4.8dB NF, -69dBm sensitivity, and -8dBm IIP3.