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Featured researches published by Yaohuang Huang.


electronics packaging technology conference | 2009

Challenges for extra large embedded wafer level ball grid array development

Jing-en Luan; Yonggang Jin; Kim-yong Goh; Yiyi Ma; Guojun Hu; Yaohuang Huang; Xavier Baraton

Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were indentified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.


electronics packaging technology conference | 2010

Embedded wafer level BGA (eWLB) - Multi-die

Ramasamy Anandan; Yonggang Jin; Yaohuang Huang; Kah Wee Gan; Puay Gek Chua; Yun Liu; Christian Geissler; Goh Hin Hwa

Although single die eWLB has been around for quite some time, processing of multi-die packages can pose many challenges. In multi-die eWLB package, two or more dies are placed side by side with a small gap, encapsulated by mold compound and interconnected with redistributed layers (RDL) and solder balls. The objective of this paper is to share the challenges in processing multi-die eWLB packages, potential solutions, key processes, results of die position measurements, mold filling, construction analysis, package level and board level reliability tests.


electronics packaging technology conference | 2011

Embedded Wafer Level BGA (eWLB) - extra-small and eLGA packages

Ramasamy Anandan; Yaohuang Huang; Yonggang Jin; Kah Wee Gan; Puay Gek Chua; Yun Liu; Jose Caparas Alvin

This paper discusses two types of eWLB packages. One is extra-small package and second is Embedded Land Grid Array (eLGA) package.


Archive | 2011

Embedded wafer level package for 3D and package-on-package applications, and method of manufacture

Kah Wee Gan; Yaohuang Huang; Yonggang Jin


Archive | 2010

Through hole via filling using electroless plating

Kah Wee Gan; Yonggang Jin; Yun Liu; Yaohuang Huang


Archive | 2012

METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE

Yonggang Jin; Yun Liu; Puay Gek Chua; Anandan Ramasamy; Yaohuang Huang; Kah Wee Gan


Archive | 2012

System in package manufacturing method using wafer-to-wafer bonding

How Yuan Hwang; Jay Maghirang; Yaohuang Huang; Kim-yong Goh; Phone Maw Hla; Edmond Soon


Archive | 2011

CIRCUIT MODULE WITH MULTIPLE SUBMODULES

KahWee Gan; Yaohuang Huang


Archive | 2012

Method for producing wafer level package and corresponding semiconductor package

Yonggang Jin; Yun Liu; Gek Chua Puay; Anandan Ramasamy; Yaohuang Huang; Wee Gan Kah


Archive | 2012

Electronic device including electrically conductive vias having different cross-sectional areas and related methods

Yonggang Jin; Yun Liu; Yaohuang Huang

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