Yonggang Jin

Next generation eWLB (embedded wafer level BGA) packaging

Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. “Fan-in” (FI)-WLP typically has a limitation to be less than 6x6mm in order to pass board level reliability requirements such as drop test and temperature cycle due to the mismatch of Si material properties to the PCB. However, the “Fan-out” (FO)-WLP, has been developed and introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. The most prominent type of FO-WLP is the eWLB technology (embedded Wafer Level Ball Grid Array). Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in next generation eWLB technologies including multi-RDL, thin eWLB and extra large eWLB as well as double-side with vertical interconnection. These key technologies of next generation eWLB enable 3D eWLB applications such as SoW (SiP on Wafer) and 3D SiP. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. The process flow of next generation eWLB fabrication, assembly and packaging challenges will be discussed. This paper will also present some of the achievements in package reliability, mechanical characterization and performance.

Mechanical characterization of next generation eWLB (embedded wafer level BGA) packaging

Integrated Circuits fabricated on silicon are assembled in different forms of electronic packages and are used extensively in electronic products such as personal, portable, healthcare, entertainment, industrial, automotive, environmental and security systems. Current and future demand for these electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in component level and board level reliability of next generation eWLB technologies including multi-RDL, thin eWLB, extra large eWLB with multi-chip. Standard JEDEC tests were carried out to investigate component level reliability and both failure analysis was performed to investigate potential structural defects. Daisychain eWLBs were assembled with different package size and different configuration as like thin or multi-RDL or multi-die. Test vehicles were also tested for drop and TCoB (Temperature on Board) reliability in industry standard test conditions. Next generation test vehicles passed both drop and TCoB tests. There was more than 50% improvement of characteristic lifetime with thinned eWLB in TCoB test because of its enhanced flexibility of package. This paper also presents study of package warpage behavior with temperature profile which is important for understanding of mechanical behavior of next generation 3D eWLBs.

Challenges for extra large embedded wafer level ball grid array development

Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were indentified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.

Development of advanced fan-out wafer level package (embedded wafer level BGA)

With reducing of silicon techno, the pitches and pads at the chip to package interface become important factor. This drives interconnection toward to fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. Fan-out WLP has the potential to realize any number of interconnects at any shrink stage of the wafer node technology.

Development of advanced fan-out wafer level package (embedded Wafer Level BGA) packaging

With reducing of silicon techno, the pitches and pads at the chip to package interface become important factor. This drives interconnection toward to fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. Fan-out WLP has the potential to realize any number of interconnects at any shrink stage of the wafer node technology. Fan-out WLP is one of key advanced packages because of advantages of higher number of I/Os, process easiness and integration flexibilities. Furthermore, it enables to integrate mUltiple dies vertically and horizontally in one package without using substrates. Thus, recently Fan-out WLP technology is moving forward to next generation packages, such as multi-die, low profile package and 3D SiP. This paper reports developments of next generation Fanout WLP for advanced packaging solutions .. A new portfolio of next generation package configurations: small outline Fanout WLP, double-side 3D Fan-out WLP and eWLL (embedded Wafer Level Land Grid Array) are developed and characterized. And the reliability study was carried out in depth by experimental approaches. Successful reliability characterization results on different package configurations are reported that demonstrate next generation Fan-out WLP as an enabling technology for miniaturized, fine pitch, high density 3D and advanced silicon packaging solutions.

Development and characterization of next generation eWLB (embedded Wafer Level BGA) packaging

The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. eWLB is one of key advanced packages because of advantages of higher number of I/Os, process easiness and integration flexibilities. Furthermore, it enables to integrate multiple dies vertically and horizontally in one package without using substrates. Thus, recently eWLB technology is moving forward to next generation packages, such as multi-die, low profile package and 3D SiP. This paper reports developments of next generation eWLB for advanced packaging solutions. A new portfolio of next generation package configurations: small outline eWLB, double-side 3D eWLB and eWLL (embedded Wafer Level Land Grid Array) are developed and characterized. And the reliability study was carried out in depth by experimental approaches. Successful reliability characterization results on different package configurations are reported that demonstrate next generation eWLB as an enabling technology for miniaturized, fine pitch, high density 3D and advanced silicon packaging solutions.

Advanced packaging solutions of next generation eWLB technology

The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology.

Embedded wafer level BGA (eWLB) - Multi-die

Although single die eWLB has been around for quite some time, processing of multi-die packages can pose many challenges. In multi-die eWLB package, two or more dies are placed side by side with a small gap, encapsulated by mold compound and interconnected with redistributed layers (RDL) and solder balls. The objective of this paper is to share the challenges in processing multi-die eWLB packages, potential solutions, key processes, results of die position measurements, mold filling, construction analysis, package level and board level reliability tests.

Thermal cycling reliability assessment and enhancement of embedded wafer level LGA packages for power applications

With great feasibility and flexibility for growing I/Os, multi-chips and system integration, the emerging fan-out embedded Wafer Level BGA (eWLB) technology is regarded as a much more favorable packaging solution compared with its traditional counterparts, i.e. fan-in WLP or BGA technology. The relentless trend of ever increasing integrated circuit chip functionality and decreasing chip dimensions for miniaturization of products have led to less chip real estate and intense heat dissipation. While eWLB technology has well addressed the routing problems associated with the former, its intrinsic ineffectiveness of reducing the spreading thermal resistance of the shrunk die has limited its application to low power devices. As a result, Quad Flat No-Lead (QFN) is often a packaging technology of choice for those applications as QFN is a lead frame based package which offers thermal and electrical enhancement with its exposed die pad on the bottom of the package surface. The exposed die pad not only provides an efficient heat path to the PCB, but also enables stable grounding with electrical connection through a conductive die attach material. To bridge the gap between the eWLB and QFN concept so that both of their advantages can be retained, STMicroelectronics has recently come up with a QFN-like eWLB package known as embedded wafer level LGA (eWLL) with low profile, high pin count and excellent thermal and electrical performance. This paper initially investigated the solder joint reliability of the eWLL packages under board level Accelerated Thermal Cycling (ATC) test through Finite Element Analysis (FEA). Experiments were then carried out to assess the accuracy of the FEA model. It was found that the predictions made by the FEA simulation correlated very well with the actual test results. The validated FEA model was then extended to study the effect of a wide range of design variables on the board level reliability of the eWLL packages. The results of the numerical analysis are compared and discussed in details.

Embedded Wafer Level BGA (eWLB) - extra-small and eLGA packages

This paper discusses two types of eWLB packages. One is extra-small package and second is Embedded Land Grid Array (eLGA) package.