Yasuhiro Kosasayama

Two-million-pixel SOI diode uncooled IRFPA with 15μm pixel pitch

We report the development of a 2-million-pixel, that is, a 2000 x 1000 array format, SOI diode uncooled IRFPA with 15 μm pixel pitch. The combination of the shrinkable 2-in-1 SOI diode pixel technology, which we proposed last year [1], and the uncooled IRFPA stitching technology has successfully achieved a 2-million-pixel array format. The chip size is 40.30 mm x 24.75 mm. Ten-series diodes are arranged in a 15 μm pixel. In spite of the increase to 2-million-pixels, a frame rate of 30 Hz, which is the same frame rate as our former generation (25 μm pixel pitch) VGA IRFPA, can be supported by the adoption of readout circuits with four outputs. NETDs are designed to be 60 mK (f/1.0, 15 Hz) and 84 mK (f/1.0, 30 Hz), respectively and a τth is designed to be 12 msec. We performed the fabrication of the 2-million-pixel SOI diode uncooled IRFPAs with 15 μm pixel pitch, and confirmed favorable diode pixel characteristics and IRFPA operation where the evaluated NETD and τth were 65 mK (f/1.0, 15 Hz) and 12 msec, respectively.

640 x 480 pixel uncooled infrared FPA with SOI diode detectors

This paper describes the structure and performance of a 25-micron pitch 640 x 480 pixel uncooled infrared focal plane array (IR FPA) with silicon-on-insulator (SOI) diode detectors. The uncooled IR FPA is a thermal type FPA that has a temperature sensor of single crystal PN junction diodes formed in an SOI layer. In the conventional pixel structure, the temperature sensor and two support legs for thermal isolation are made in the lower level of the pixel, and an IR absorbing structure is made in the upper pixel level to cover almost the entire pixel area. The IR absorption utilizes IR reflections from the lower level. Since the reflection from the support leg portions is not perfect due to the slits in the metal reflector, the reflection becomes smaller as the support leg section increases in reduced pixel pitches. In order to achieve high thermal isolation and high IR absorption simultaneously, we have developed a new pixel structure that has an independent IR reflector between the lower and upper levels. The structure assures perfect IR reflection and thus improves IR absorption. The FPA shows a noise equivalent temperature difference (NETD) of 40 mK (f/1.0) and a responsivity non-uniformity of less than 0.9%. The good uniformity is due to the high uniformity of the electrical characteristics of SOI diodes made of single crystal silicon (Si). We have confirmed that the SOI diodes architecture is suitable for large format uncooled IR FPAs.

Uncooled IRFPA with chip scale vacuum package

We have developed an uncooled IRFPA with a chip scale vacuum package and succeeded in obtaining excellent IR images of less than 60 mK in NETD. This package consists of a device chip and a silicon lid. The chip in this study is a 160 x 120 SOI diode IRFPA with a 25 μm pixel pitch. The size of the package is 14.5(L) x 13.5(W) x 1.2(H) mm. The gap between the device chip and the lid is controlled by the thickness of the vacuum sealing material. The lid is prepared by a wafer process and diced just before vacuum sealing. We use DLC (diamond like carbon) as the AR coat because of its high IR transmittance and high endurance in the wafer process. DLC films are deposited on both sides of the silicon lid wafer, and then a ring-shaped metal pattern for solder bonding is formed on one side of the lid wafer. Solder is mounted on the metal pattern by a molten solder ejection method. The patterned thin-film getter is formed on the lid wafer. Because of the use of patterned thin-film getter, there is no need to form a cavity on the lid to allow installation of getter or to insert a spacer between the device chip and the lid. Then the lid wafer is diced into individual lids. The device wafer and the lids are set in a vacuum chamber, which has a heater to melt the solder, so as to pair each die and lid. After pumping the chamber, the patterned thin-film getters are activated and then the lids are bonded simultaneously to the device wafer. Finally the device wafer is diced into individual chips. The measured pressure of the package is less than 0.5 Pa which is sufficient for obtaining high thermal isolation. In this technique, only the good dies in a wafer are packaged in chip scale simultaneously. Thus, a reduction in the size and cost of the package has been achieved.

Performance of 320 x 240 uncooled IRFPA with SOI diode detectors

We reported a 320 x 240 uncooled IRFPA with 40 micrometers pitch having diode detectors fabricated on an SOI wafer. Since the fabrication process of the SOI diode detector is compatible with the silicon IC process, only a silicon IC fab is necessary for manufacture of the FPAs. This enables mass production of low cost uncooled FPAs. This paper focuses on the performance of the FPA. In the previous paper, we proposed a novel infrared absorbing structure which offers a very high fill factor. Although this structure exhibited a high infrared absorption because of interference absorbing components incorporated in the structure, large thermal capacitance was an issue. Thus we have improved the infrared absorbing structure in the newly developed FPA. The improved absorbing structure has been devised making use of reflection of metal interconnections including diode metal straps. A thermal time constant of 17 msec has been achieved without degrading the responsivity compared with the conventional absorbing structure.

Pixel scaling for SOI-diode uncooled infrared focal plane arrays

Pixel scaling for SOI diode uncooled infrared focal plane arrays (IRFPAs) was investigated in order to achieve the realization of small size and low cost IRFPAs. Since the SOI diode pixel has two different layers -- one for the temperature sensor and the thermal isolation structure, and the other for the infrared absorption structure -- each layer can be independently designed. Hence, a high fill factor can be maintained when reducing pixel size without changing the basic structure of the pixel, which is advantageous in reducing the pixel size. In order to verify this, the authors have developed an SOI diode IRFPA with the pixel size of 28 μm x 28 μm which is 49% of the previous pixel size (40 μm x 40 μm) and achieved a noise equivalent temperature difference (NETD) of 87 mK. In order to further reduce the pixel size and to improve device sensitivity, we propose a new pixel structure. In this structure, a reflector is fabricated between the infrared absorption structure and support legs. Therefore, the infrared rays which are incident on the support legs, which do not sufficiently function as a reflector, can be used effectively. A new pixel structure with a pixel size of 25 μm x 25 μm was fabricated and realized the thermal conductance of 1.0 x 10-8 W/K and the infrared absorption structure was then verified for its effectiveness.

Novel readout circuit architecture realizing TEC-less operation for SOI diode uncooled IRFPA

We have developed a novel readout circuit architecture realizing a TEC-less (Thermo-Electric Cooler) operation for an SOI diode uncooled infrared focal plane array (IRFPA). Through the fabrication of an SOI diode uncooled 320 x 240 IRFPA adopting the readout circuit architecture with our existing 25μm pixel-pitch technology, we demonstrate that the variation of the output DC level of the pixels is successfully suppressed in environmental temperatures from -10°C to 50°C. The developed TEC-less technology greatly enhances the ability of the SOI diode uncooled IRFPA, which inherently possesses excellent uniformity and low noise features.

Silicon infrared focal plane arrays

Using Si VLSI technology, we can fabricate various kinds of infrared focal plane arrays (FPAs) which cover spectral bands from short wavelength infrared to long wavelength infrared. The Si-based technology offers many attractive features, such as monolithic integration, high uniformity, low noise, low cost, and high productivity. We have been developing Si-based infrared FPAs for more than 20 years and have verified their usefulness.

Implementation of SOI diode uncooled IRFPA in TEC-less and shutter-less operation

We develop a shutter-less method for replacing mechanical shutters. To verify the effectiveness of the proposed method, we fabricated a silicon-on-insulator (SOI) diode uncooled 320 × 240 infrared focal plane array (IRFPA) with 17 μm pixel pitch utilizing a circuit architecture that achieves thermo-electric cooling (TEC)-less operation. Furthermore, we fabricated a prototype uncooled IR camera that implements the proposed method and verified favorable camera operation. The temperature behavior of our proposed SOI diode is highly uniform and predictable, which enables simpler device modeling and consequently simpler TEC-less and shutter-less operation.

160×120 Uncooled IRFPA for Small JR Camera

We have developed a 160 times 120 SOI (silicon on insulator) diode uncooled IRFPA (Infrared Focal Plane Array) with 25 mum pixel pitch for a small IR camera. The IRFPA has a highly responsive pixel structure and is packaged in a chip scale vacuum package (CSVP) in order to reduce the package size. The size of the package is 14.5(L) times 13.5(W) times 1.2(H) mm. An infrared image of less than 60 mK in NETD (Noise Equivalent Temperature Difference) with f/1.0 optics has been obtained by the developed IRFPA.

A Variable Channel-Size MOSFET with Lightly Doped Drain Structure

We propose a metal oxide semiconductor field-effect transistor (MOSFET) whose channel size can be modified by applying control voltage. The variable-channel-size MOSFET (VS-MOS) has a control gate between the main gate and the source/drain. The control gate possesses a gap at its end in the active region. Owing to this unique layout, the VS-MOS achieves continuous modulation of effective channel size and can be fabricated using the conventional complementary MOS (CMOS) fabrication process. Results of test device fabrication show that the channel size modulation can be enhanced by employing the lightly doped drain (LDD) structure. It is also shown that the logic threshold can be controlled in a CMOS inverter composed of the VS-MOS.