Yasuhiro Ohtsuka
University of Tokyo
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Featured researches published by Yasuhiro Ohtsuka.
international conference on image processing | 1999
Takayuki Hamamoto; R. Ooi; Yasuhiro Ohtsuka; Kiyoharu Aizawa
We have been investigating an integration of sensing and compression on an image sensor. The compression sensor reduces the number of pixels in the image signal that has to be readout from the sensor. Therefore, the compression sensor can capture the images at the higher pixel rate which the traditional sensor can not handle. In this paper, we present a compression sensor which has 228/spl times/128 pixels. The processing circuits of the sensor can be operated at 5000 frames/second. We also describe the experimental results of two real-time image processing systems by using the compression sensor. They are a reconstruction circuit by using FPGA and a stereo image processing system for tracking of a moving object.
international conference on image processing | 1997
Kiyoharu Aizawa; Takayuki Hamamoto; Yasuhiro Ohtsuka; Mitsutoshi Hatori; Masahide Abe
In order to enhance performance of an image sensor, we have been investigating a novel integration of compression and sensing. By this integration, the image signal that has to be readout from the sensor is significantly reduced. Thus, the integration can consequently leads to high pixel rate sensing. The compression scheme we make use of is conditional replenishment that detects and encodes moving areas. We have developed prototypes based on two different architectures, that are pixel parallel and column parallel architectures. We present the two prototypes and their comparisons, and show the results obtained by them.
international symposium on circuits and systems | 1998
Yasuhiro Ohtsuka; Takayuki Hamamoto; Kiyoharu Aizawa; Mitsutoshi Hatori
We propose a new sampling control system for an image sensor. Contrary to the random access pixels, the proposed sensor is able to read out spatially variant pixels at high speed, without inputting pixel address for each access. The sampling positions can be changed dynamically by rewriting the sampling position memory. Since the proposed sensor has sampling position memory that stores the sampling control order, it is able to easily control sampling position. We can achieve any spatially varying sampling patterns.
international conference on image processing | 1998
Takayuki Hamamoto; Yasuhiro Ohtsuka; Kiyoharu Aizawa
We have been investigating a novel integration of sensing and compression on an image sensor. By integration, the number of pixels in the image signal that has to be readout from the sensor can be significantly reduced, and the integration, can consequently increase the pixel rate of the sensor. We present a new compression sensor which has 128/spl times/128 pixels. We have made the prototype based on a column parallel architecture and improved the processing circuits of the new prototype to achieve lower power dissipation and higher processing speed in comparison with our previous prototypes. It is verified that the processing circuits can be operated at 5000 frames/second.
international symposium on circuits and systems | 2001
Yasuhiro Ohtsuka; I. Ohta; Kiyoharu Aizawa
This paper presents a new image sensor with programmable multiresolution readout capability. The proposed image sensor can output data at varying resolutions. Differing to our previously reported spatially variant sampling sensor, which sub-samples without filtering, in the multiresolution sensor blocks of the pixels are averaged and read out so the new sensor does not suffer from aliasing effects. The resolution can be controlled by varying the block size. We made a prototype of 64/spl times/64 pixels.
The Journal of The Institute of Image Information and Television Engineers | 1999
Yasuhiro Ohtsuka; Takayuki Hamamoto; Kiyoharu Aizawa; Mitsutoshi Hatori
We propose a new spatially variant sampling control system integrated on an image sensor. This sensor can read out spatially variant pixels at high speed, without inputting pixel address for each access. Since it has a memory array that keeps the pixel position to be sampled, the sampling position can be dynamically changed by rewriting the memory array. It can achieve any spatially varying sampling patterns. We show the principles, circuit designs, a prototype of the sensor, and results obtained by the prototype.
international conference on image processing | 1998
Yasuhiro Ohtsuka; Takayuki Hamamoto; Kiyoharu Aizawa; Mitsutoshi Hatori
We propose a new sampling control system integrated on an image sensor. Contrary to the conventional random access pixels, the proposed sensor is able to read out spatially variant pixels at high speed, without inputting pixel address for each access. The sampling positions can be changed dynamically by rewriting the sampling position memory. Since the proposed sensor has an array memory that keeps the pixel position to be sampled. The sampling position can be dynamically changed by rewriting the memory array. It can achieve any spatially varying sampling patterns. We have made a first prototype and show results obtained by the prototype.
The Journal of The Institute of Image Information and Television Engineers | 1998
Yasuhiro Ohtsuka; Takeo Ozeki; Takayuki Hamamoto; Kiyoharu Aizawa; Mitsutoshi Hatori; Masahide Abe
筆者らはリアルタイム信号処理におけるデータ転送部のボトルネックの解消を目的として, 圧縮機構を搭載した画素並列処理センサを検討, 試作した.本センサには閾値を制御することにより転送部報量を制御する定レート制御機能が搭載されている.本稿では, この定レート制御機能の検証結果について述べる.
SYBEN-Broadband European Networks and Electronic Image Capture and Publishing | 1998
Takayuki Hamamoto; Yasuhiro Ohtsuka; Kiyoharu Aizawa
In order to enhance the performance of image sensing, we have been investigating a novel image sensor which compresses image signal on the sensor focal plane. By the integration of sensing and compression, number of pixels in the image signal that has to be readout from the sensor can be significantly reduced, and the integration can consequently increase the pixel rate of the sensor. In this paper, we describe a new prototype sensor based on a column parallel architecture which has 128 X 128 pixels. We have improved the processing circuits of the new prototype to achieve much lower power dissipation and higher processing speed. We have verified that the processing circuits can be operated at 5000 frames/second.
Archive | 2002
Kiyoharu Aizawa; Yasuhiro Ohtsuka