Yasunari Umemoto

A bipolar mechanism for alpha-particle-induced soft errors in GaAs integrated circuits

The alpha-particle-induced collected charge in undoped LEC semi-insulating GaAs is measured in n/sup +/-i-n/sup +/ and n/sup +/-p-n/sup +/ isolation structures and is compared with the results of an analytical model based on a bipolar mechanism. In n/sup +/-i-n/sup +/ isolation structures, a collected-storage multiplication phenomenon induced by alpha-particle incidence is observed. The measured collected charge is about three times the alpha-particle-generated charge. This phenomenon can be attributed to charge transfer between two adjacent n/sup +/ regions. The dominant charge-collection process continues for 2.4 ns in n/sup +/-i-n/sup +/ isolation structures, but in n/sup +/-p-n/sup +/ isolation structures, it stops within 0.8 ns. The measured collected charge decreases as the isolation gap and background acceptor concentration increase. These experimental results can be explained semiquantitatively by the analytical model. This suggests that the primary mechanism of soft errors in GaAs ICs is a bipolar mechanism. >

Improvement of alpha-particle-induced soft-error immunity in a GaAs SRAM by a buried p-layer

Alpha-particle-induced soft-error immunity in a 1-kB GaAs SRAM was improved by a buried p-layer, which was formed in isolation regions as well as in FET regions and was designed to be completely depleted. The mean time between failures exceeded 10/sup 4/ at an alpha-particle fluence of about 2.0*10/sup 4/ cm/sup -2/-s/sup -1/ with a 1.0- mu Ci/sup 241/Am source. The alpha-particle energy had a peak at 4.0 MeV and was distributed from nearly 0 to 4.6 MeV. This value is five orders of magnitude better than that for a conventional SRAM without a buried p-layer. This improvement in the soft-error immunity can be achieved without increasing the access time or the power consumption by depleting the p-layer completely. Also discussed is the possibility of using a conductive p-layer scheme for higher integration of GaAs SRAMs. >

Pseudomorphic power HEMT with 53.5% power-added efficiency for 1.9-GHz PHS standards

We demonstrate a power-added efficiency of 53.5% at a very low idling current of 13 mA with a drain bias of 3 V in a proposed power amplifier. This amplifier meets the standards for the 1.9 GHz Japanese Personal Handy-phone System (PHS) which requires highly linear amplifiers, and this is the highest power-added efficiency and the lowest idling current so far reported. The proposed power amplifier uses a pseudomorphic high electron mobility transistor (PHEMT) which provides high transconductance, high linearity, and low idling current operation. This PHEMT was fabricated by using advanced power-device technology: the GaAs-InGaAs-GaAs PHEMT structure has a 0.35 /spl mu/m gate made using phase-shifting lithography and a high In mole ratio (0.35) InGaAs channel.

2 V-operation pseudomorphic power HEMT with 62% power-added efficiency for cellular phones

We demonstrate maximum power-added efficiency of 62% with a 2-V drain bias at L-band frequencies on a pseudomorphic high electron mobility transistor (PHEMT) for use in analog cellular phones. This PHEMT is fabricated by advanced power-device technology featuring a GaAs-InGaAs-GaAs PHEMT structure with a low-temperature process and gate-stress compensation. Power performance evaluated under the Japanese standards for 1.5-GHz personal digital cellular phones (PDC) exhibits a very high power-added efficiency of 51% (54%) with an output power of 0.8 W (1.7 W) at a 2-V (3-V) drain bias. The adjacent-channel leakage is 50 dBc at 1.5 GHz +/-50 KHz when tested at this output power. These results indicate that the proposed PHEMT power device is highly suitable for use in analog and digital cellular phone systems.<<ETX>>

Selective Growth of Ultra-low Resistance GaAs/lnGaAs for High Performance lnGaAs FETs

To minimize the source resistance of a doped-channel InGaAs heterostructure FET grown on a GaAs substrate, GaAs, InGaAs and InAs selective growth conditions are studied by metalorganic vapor phase epitaxy (MOVPE). It is found that the lowest growth temperatures with complete selectivity for InGaAs (indium composition less than 0.2) and InAs are 540 and 400°C, respectively. The contact resistance at the regrown interface measured with the transmission line model (TLM), is minimized to 5 × 10-9 ω cm2 when the Si-doped GaAs is regrown using a side contact structure. However, the contact resistance increases as the In composition in the regrown InGaAs increases. This might be due to the strain or dislocations caused by lattice mismatching between GaAs and InGaAs.

Very Fast Integrated Optoelectronic Logic for Parallel Computation Using Photodiode Gates

A new configuration of an integrated optoelectronic logic unit using GaAs photodiode gates is proposed. Implementation of AND and EOR logic units are performed monolithically using GaAs/AlGaAs multilayer structures. Discussions are made on the realization of the full adder by means of optical feedback between the photodiode logic array and the surface emitting diode laser array.

Alpha-particle-induced soft-error mechanism in semi-insulating GaAs substrate

The primary mechanism which causes alpha-particle-induced soft error in GaAs ICs is clarified. A description is given of a charge-collection model that includes a bipolar mechanism. It is shown that mechanism causes about 90% of the total collected charge in the n-i-n isolation structure and that suppressing it is the most effective way to prevent soft error in GaAs ICs. Experimental results are presented and shown to agree with predictions based on the model. >

GaAs FET with a degenerate semiconductor gate

A new GaAs FET structure has been proposed and examined experimentally in which the gate material is degenerate p-Al0.3Ga0.7As fabricated directly on to a p-type layer of undoped semi-insulating GaAs substrates. Obtained transconductance was 207mS/mm under the gate bias of 2V for the gate length of2\microm and the onset voltage of the gate leakage current was 0.5-0. 6V higher than that of MESFETs. These characteristics were explained by the presence of an n-type inversion layer located at p-AlGaAs/p-GaAs interface. Temperature dependence of the drain current leads to a conclusion that the Fermi level was pinned at the interface states 0.475eV above the valence band.

0.2/spl mu/m Gate Aigaas/gaas Higfet (Heterostructure Insulated gate FET) with a

Summary form only given. A GaAs HIGFET with a K value of 1 A/V/sup 2//mm has been developed for application to high-speed LSIs. A description is presented of the three essential processes for fabricating this HIGFET: (1) a gate process using a

0.2μm Gate AlGaAs/GaAs HIGFETt (Heterostructure Insulated gate FET) with a (111) face of n + -GaAs selectively grown by MOCVD

A new GaAs HIGFET with K-value of 1A/V 2 /mm has been developed for application to high-speed LSIs. This paper describes three essential processes for fabricating this HIGFET: (1) a new gate process using a (111) face appearing on selectively-grown n + -GaAs, for both achieving a 0.2-μm gate and reducing the short channel effect; (2) a highly-doped GaAs channel grown by MBE, for increasing the K-value; and (3) a technique for establishing side contact between the n + -GaAs and the n-GaAs channel, for minimizing a source resistance.