Yasushi Yuminaka
Gunma University
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Publication
Featured researches published by Yasushi Yuminaka.
international symposium on multiple valued logic | 2007
Yasushi Yuminaka; Kazuyoshi Yamamura
The performance of recent high-speed VLSI systems is significantly limited by the interconnection bandwidth inside/between chips relative to individual transistor performance. However, the attenuation or deterioration of signals, arises from physical phenomena in transmission lines, restricts the maximum frequency at which the signal can transmit. This paper investigates data recovery techniques especially for multiple-valued data transmission in order to achieve high-speed data transmission in VLSI systems. We discuss various types of equalization techniques including inductive-coupling wireless communication to compensate for the frequency-dependent loss of wiring, resulting in improving a data transfer rate.
international conference on electronics circuits and systems | 1999
M.A. Mohamed Zin; Haruo Kobayashi; Kensuke Kobayashi; J.-I. Ichimura; Hao San; Yoshitaka Onaya; Y. Kimura; Yasushi Yuminaka; Yoshisato Sasaki; Kouji Tanaka; Fuminori Abe
This paper describes the design of a high-speed CMOS track/hold circuit in front of an ADC. The track/hold circuit employs differential open-loop architecture, very linear source follower input buffers, NMOS sampling switches and bootstrap sampling-switch driver circuits for high-speed operation with 3.3 V supply voltage. SPICE simulations with MOSIS 0.35 /spl mu/m CMOS BSIM 3v3 parameters showed that it achieves the signal-to-(noise+distortion)-ratio (SNDR) of more than 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mW power consumption. A test circuit was fabricated with MOSIS 0.8 /spl mu/m CMOS process and its measured results show that the proposed circuit topology performs a track/hold operation.
international symposium on multiple-valued logic | 2012
Yasushi Yuminaka; Masaaki Okui
This paper proposes multiple-valued pulse position modulation (MVPPM) techniques to achieve highly efficient data transmission in VLSI systems. The MVPPM coding employs 2-dimensional information representation in both time and amplitude domain to increase data rates. This time-domain information processing uses timing resolution, and therefore fits well with advanced high-speed low-voltage CMOS processes. An MVPPM transceiver is designed and simulated using SPICE to demonstrate the capability of compensating for deterioration of signals caused by interconnections.
Ultrasonic Imaging | 2015
Yoshiki Yamakoshi; Toshihiro Kasahara; Tomohiro Iijima; Yasushi Yuminaka
A wavefront reconstruction method for a continuous shear wave is proposed. The method uses ultrasound color flow imaging (CFI) to detect the shear wave’s wavefront. When the shear wave vibration frequency satisfies the required frequency condition and the displacement amplitude satisfies the displacement amplitude condition, zero and maximum flow velocities appear at the shear wave vibration phases of zero and π rad, respectively. These specific flow velocities produce the shear wave’s wavefront map in CFI. An important feature of this method is that the shear wave propagation is observed in real time without addition of extra functions to the ultrasound imaging system. The experiments are performed using a 6.5 MHz CFI system. The shear wave is excited by a multilayer piezoelectric actuator. In a phantom experiment, the shear wave velocities estimated using the proposed method and those estimated using a system based on displacement measurement show good agreement.
international symposium on multiple valued logic | 2008
Yasushi Yuminaka; Yasunori Takahashi
This paper presents a new equalization technique based on a pulse-width modulation (PWM) pre-emphasis method which utilizes time-domain information processing to increase the data rate for a given bandwidth of VLSI interconnection. The pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower voltage headroom. We discuss new time-domain pre-emphasis techniques especially for multiple-valued data transmission in order to achieve high-speed data transmission in VLSI systems.
Japanese Journal of Applied Physics | 2015
Yoshiki Yamakoshi; Atsushi Yamamoto; Toshihiro Kasahara; Tomohiro Iijima; Yasushi Yuminaka
We have proposed a quantitative shear wave imaging technique for continuous shear wave excitation. Shear wave wavefront is observed directly by color flow imaging using a general-purpose ultrasonic imaging system. In this study, the proposed method is applied to experiments in vivo, and shear wave maps, namely, the shear wave phase map, which shows the shear wave propagation inside the medium, and the shear wave velocity map, are observed for the skeletal muscle in the shoulder. To excite the shear wave inside the skeletal muscle of the shoulder, a hybrid ultrasonic wave transducer, which combines a small vibrator with an ultrasonic wave probe, is adopted. The shear wave velocity of supraspinatus muscle, which is measured by the proposed method, is 4.11 ± 0.06 m/s (N = 4). This value is consistent with those obtained by the acoustic radiation force impulse method.
international symposium on multiple-valued logic | 2009
Yasushi Yuminaka; Yasunori Takahashi; Kenichi Henmi
This paper describes a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower voltage headroom. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects.
international symposium on multiple valued logic | 2000
Yasushi Yuminaka; Osamu Katoh; Yoshisato Sasaki; Takafumi Aoki; Tatsuo Higuchi
This paper investigates a multiple-valued code-division multiple access (MV-CDMA) technique to achieve efficient data transmission and processing in VLSI systems. CDMA employs a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier. Orthogonal property of m-sequences enables us to multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission. With reduced interconnection. Also, randomness of m-sequences offers the high tolerance to noise interference. In the case of conventional CDMA, however, co-channel interference due to carrier phase offset error severely restricts the available number of multiplexing. In order to eliminate carrier phase offset error, we propose a new class of multiple-valued m-sequences. An application example of neural networks is discussed to demonstrate the feasibility of MV-CDMA in terms of reducing interconnections and eliminating co-channel interference.
Analog Integrated Circuits and Signal Processing | 2001
Haruo Kobayashi; Mohd Asmawi Mohamed Zin; Kazuya Kobayashi; Hao San; Hiroyuki Sato; Jun-Ichi Ichimura; Yoshitaka Onaya; Naoki Kurosawa; Yasuyuki Kimura; Yasushi Yuminaka; Kouji Tanaka; Takao Myono; Fuminori Abe
This paper describes the design of a high-speed CMOSTrack/Hold circuit in front of an ADC. The Track/Hold circuit employsdifferential open-loop architecture, very linear source follower inputbuffers, NMOS sampling switches and bootstrap sampling-switch drivercircuits for high-speed operation with 3.3 V supply voltage. SPICEsimulations with MOSIS 0.35 μm CMOS BSIM3v3 parameters showed thatit achieves a signal-to-(noise+distortion)-ratio (SNDR) of morethan 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mWpower consumption.
international symposium on multiple valued logic | 1998
Yasushi Yuminaka; Yoshisat Sasaki; Takafumi Aoki; Tatsuo Higuchi
A Wave-Parallel Computing (WPC) technique is proposed to address the interconnection problem in massively interconnected VLSI architectures. The fundamental concept is the multiplexing of several signals onto a single line using orthogonal sequences as information carriers. To reduce MUX/DEMUX circuits, we propose WPC concept which can process multiplexed data directly without decomposition. We investigate the possible implementation of WPC based on the present MOS technology, and propose the multiple valued pseudo-orthogonal m-sequence carrier generation technique. Applications of WPC to neural networks and image processing are discussed, with emphasis on the reduction in the in number of interconnections and on the noise tolerance property.