Yoshisato Sasaki

A new experimental determination of the relationship between the Hall mobility and the hole concentration in heavily doped p-type silicon

Abstract The relationship between the Hall mobility and the hole concentration in p-type silicon were experimentally investigated. Boron and gallium were used as dopants; their doping was done by either the ion implantation or the diffusion technique. It was found that the relationships for boron-doped specimens and for gallium-doped specimens for the heavily doped range are considerably different from each other. Both of these relationships are also different from the so-called Irvin curve which is well known as a standard relationship between the mobility of carriers and the impurity concentration, but the relationship for boron doping is almost consistent with that of Thurber et al., if the Hall mobility factor is reasonably taken into account.

Thermal Behavior of B, P and As Atoms in Supersaturated Si Produced by Ion Implantation and Pulsed-Laser Annealing

The heat treatment effect on supersaturated Si crystals with B, P, or As produced by high-dose ion implantation (8×1015 cm-2) and Q-switched ruby laser annealing (2.0 J/cm2) is investigated. The deactivation of excess B atoms becomes appreciable with a high-temperature heat treatment above 800°C, while deactivations of excess P and As atoms take place even at low temperatures of 300–400°C. The deactivation process of B atoms at such high temperatures was found to be a precipitation of B atoms with an activation energy of 3.2 eV using Hall effect measurements and transmission electron microscopy observation.

A high-speed CMOS track/hold circuit

This paper describes the design of a high-speed CMOS track/hold circuit in front of an ADC. The track/hold circuit employs differential open-loop architecture, very linear source follower input buffers, NMOS sampling switches and bootstrap sampling-switch driver circuits for high-speed operation with 3.3 V supply voltage. SPICE simulations with MOSIS 0.35 /spl mu/m CMOS BSIM 3v3 parameters showed that it achieves the signal-to-(noise+distortion)-ratio (SNDR) of more than 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mW power consumption. A test circuit was fabricated with MOSIS 0.8 /spl mu/m CMOS process and its measured results show that the proposed circuit topology performs a track/hold operation.

An efficient data transmission technique for VLSI systems based on multiple-valued code-division multiple access

This paper investigates a multiple-valued code-division multiple access (MV-CDMA) technique to achieve efficient data transmission and processing in VLSI systems. CDMA employs a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier. Orthogonal property of m-sequences enables us to multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission. With reduced interconnection. Also, randomness of m-sequences offers the high tolerance to noise interference. In the case of conventional CDMA, however, co-channel interference due to carrier phase offset error severely restricts the available number of multiplexing. In order to eliminate carrier phase offset error, we propose a new class of multiple-valued m-sequences. An application example of neural networks is discussed to demonstrate the feasibility of MV-CDMA in terms of reducing interconnections and eliminating co-channel interference.

Fabrication of Thin Silicon Wires by Anisotropic Wet Etching of SOI Structures

A fabrication method of thin single-crystalline silicon wires on SiO2 is reported. The wires are fabricated by anisotropic wet etching of (110) and (100) SOI wafers. We obtained a thin (110) SOI wire of 0.2 µm width and 0.2 µm height with a rectangular cross section. Since the (110) SOI wires are enclosed by a pair of ultraflat {111} side walls parallel to each other, this method has the potential to form ultranarrow wires by careful control of the etching conditions.

Enhanced Diffusion of Implanted Arsenic in Silicon at an Early Stage of Annealing

The diffusion profiles of the heavily ion-implanted arsenic (As) in silicon by short annealing time were examined by Hall effect measurements in conjunction with anodization and layer removal. The arsenic diffusion profiles obtained by computer simulation were compared with the measured results. It is shown by this comparison that the diffusion of the arsenic atoms is enhanced at an early stage of annealing.

Laser sintering of VO2 film

The conventional preparation process of VO2 temperature sensors requires the precise control of ambient atmosphere. This is one of the difficulties in their application to integrated devices. Laser sintering proved to be useful in overcoming this difficulty. Specimens of VO2 film (1.4×1.4×0.04 mm3 in size) printed on alumina substrates changed in electrical resistance by a factor of 102 at about 68 °C with increasing temperature, after exposing them, in open air, to a 2‐ms pulse beam from a ruby laser on relaxation oscillation, whose energy density was 6.5 J/cm2.

Modeling and parameter extraction technique for high-voltage MOS device

This paper presents a novel technique for modeling HV MOS devices accurately with the BSIM3v3 SPICE model. We assign different meanings from the original BSlM3v3 to three parameters. The simulated I-V characteristics using the extracted parameters match the measured results well, and the physical mechanism of HV MOS devices is clarified based on device simulations. Since our method does not change any model equations of BSIM3v3, it can be applied to any SPICE simulator on which the BSIM3v3 model runs.

Wave-parallel computing technique for neural networks based on amplitude-modulated waves

Wave-parallel computing (WPC) technique is proposed to address the interconnection problem in massively interconnected VLSI architectures required for implementing artificial neural networks. The fundamental concepts are frequency multiplexing of signals on a single line, and their wave-parallel processing without decomposition. This paper discusses the realization of a Hopfield-type fully connected neural network as an example, and shows that the WPC-based network exhibits much lower topological complexity compared with the original network. We also investigate the possible implementation of WPC based on the present MOS technology, and discuss the evaluation in terms of the degree of multiplexing and processing speed.

Two-Dimensional Localization Effect with Spin-Orbit Scattering in Arsenic Doped Polycrystalline Silicon Films

We have investigated the 3D-2D crossover of the localization effect in a system of heavily arsenic doped polycrystalline silicon films with thickness 40 to 1350 A. The films with d ≦220 A show a log T dependence of the conductance. For a 220 A film, ∼60% of the quantum correction to the conductivity is attributed to the electron-electron interaction effect, and the rest to the localization effect. Analyses of the magnetoconductance behavior have indicated that a weak spin-orbit scattering should be taken into account in the localization effect; a feature not observed in n-type bulk Si. The diffusion length of the spin-orbit scattering is estimated to be 0.28µm. The inelastic scattering time τ in for the 220 A film varies as T -0.95 , indicating that the electron-electron scattering is the dominant phase breaking process in the present dirty 2D systems.