Akiyuki Sugiyama

A new matching engine between design layout and SEM image of semiconductor device

Optical proximity correction (OPC) plays a vital role in the lithography process development of current semiconductor devices. OPC is utilized to achieve the ideal pattern shape because of the limitations of optical resolution. However, the lithography process design has become increasingly more complex due to the abundant use of OPC features. Hence, metrology requests for CD-SEM have also become more complex and diverse in order to characterize the critical OPC models. The number of measurement points for OPC model evaluation has increased to several hundred points per layer, and metrology requests for realized pattern shapes on the wafer are no longer simple one-dimensional measurements. Metrology requests include not only the traditional line width measurements, but also edge placement error (EPE) and corner rounding to identify line end shortening. Several researchers have proposed using the design layout as a template instead of the SEM image for the recipe creation of CD-SEM and EPE measurement. However, it is very difficult to achieve good matching results between the design layout and the SEM image in practical processing times. Hitachi High-Technologies has developed a robust and quick matching engine between the design layout and SEM image bitmap. The new system, incorporating this new matching engine, can automatically create a practical recipe from the coordinate information of measurement point and the design layout information, such as GDSII. As a result, the new system can vastly reduce the amount of time and number of operations required to generate a several-hundred point CD-SEM recipe for OPC evaluation. This study demonstrates the capability and presents evaluation results of this new matching engine. This new capability has proven to be a viable solution for OPC evaluation, and its efficiency will allow for quicker information turns between design and manufacturing.

Advanced CD-SEM metrology for pattern roughness and local placement of lamellar DSA

Directed self-assembly (DSA) applying chemical epitaxy is one of the promising lithographic solutions for next generation semiconductor device manufacturing. We introduced Fingerprint Edge Roughness (FER) as an index to evaluate edge roughness of non-guided lamella finger print pattern, and found its correlation with the Line Edge Roughness (LER) of the lines assembled on the chemical guiding patterns. In this work, we have evaluated both FER and LER at each process steps of the LiNe DSA flow utilizing PS-b-PMMA block copolymers (BCP) assembled on chemical template wafers fabricated with Focus Exposure Matrix (FEM). As a result, we found the followings. (1) Line widths and space distances of the DSA patterns slightly differ to each other depending on their relative position against the chemical guide patterns. Appropriate condition that all lines are in the same dimensions exists, but the condition is not always same for the spaces. (2) LER and LWR (Line Width Roughness) of DSA patterns neither depend on width nor LER of the guide patterns. (3) LWR of DSA patterns are proportional to the width roughness of fingerprint pattern. (4) FER is influenced not only by the BCP formulation, but also by its film thickness. We introduced new methods to optimize the BCP formulation and process conditions by using FER measurement and local CD valuation measurement. Publisher’s Note: This paper, originally published on 2 April 2014, was replaced with a corrected/revised version on 14 May 2014. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.

Concerning the influence of pattern symmetry on CD-SEM local overlay measurements for double patterning of complex shapes

We have developed a new local overlay measurement technique on actual device patterns using critical dimension scanning electron microscope (CD-SEM), which can be applied to 2D device structures such as an SRAM contact hole array or more complex shapes. CD-SEM overlay measurement can provide additional local overlay information at the site of device patterns, complementary to the conventional optical overlay data. The methodology includes the use of symmetrically arranged patterns to cancel out many process effects and reduce measurement uncertainty. The developed methodology was applied to local overlay measurement of double patterning contact hole layers of leading edge devices. Local overlay distribution was successfully captured on device structures on different length scale, and the result shows the possibility of assessing process induced shift on device structures and collecting denser sampling for better intra-chip overlay control. The measurement uncertainty of CD-SEM overlay metrology was assessed by comparing with conventional optical overlay metrology for 1D and 2D structures. Very good correlation was confirmed between SEM and optical overlay metrology with net residual error of ~1.1nm. Measurement variation associated with pattern roughness was analyzed for 1D structure, and identified as one of major variation sources for CD-SEM overlay metrology.

New method of Contour based mask shape compiler

We have developed a new method of accurately profiling a mask shape by utilizing a Mask CD-SEM. The method is intended to realize high accuracy, stability and reproducibility of the Mask CD-SEM adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD measurement. In comparison with a conventional image processing method for contour profiling, it is possible to create the profiles with much higher accuracy which is comparable with CD-SEM for semiconductor device CD measurement. In this report, we will introduce the algorithm in general, the experimental results and the application in practice. As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC (Optical Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the view point of DFM (Design for Manufacturability), a dramatic increase of data processing cost for advanced MDP (Mask Data Preparation) for instance and surge of mask making cost have become a big concern to the device manufacturers. In a sense, it is a trade-off between the high accuracy RET and the mask production cost, while it gives a significant impact on the semiconductor market centered around the mask business. To cope with the problem, we propose the best method for a DFM solution in which two dimensional data are extracted for an error free practical simulation by precise reproduction of a real mask shape in addition to the mask data simulation. The flow centering around the design data is fully automated and provides an environment where optimization and verification for fully automated model calibration with much less error is available. It also allows complete consolidation of input and output functions with an EDA system by constructing a design data oriented system structure. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

Critical dimension scanning electron microscope local overlay measurement and its application for double patterning of complex shapes

We have developed a new local overlay measurement technique on actual device patterns using a critical dimension scanning electron microscope (CD-SEM), which can be applied to two-dimensional (2D) device structures such as a static random access memory contact hole array. CD-SEM overlay measurement can provide additional local overlay information at the site of device patterns, complementary to the optical overlay. The methodology includes the use of pattern symmetry to cancel out many process effects and reduce measurement uncertainty. CD-SEM overlay metrology was compared with conventional optical overlay metrology in terms of measurement uncertainty and overlay model analysis, and very good correlation was confirmed. The developed methodology was applied to local overlay measurement of double patterning contact hole layers of leading edge devices. The local overlay distribution was obtained across the device area, and spatial correlation of the overlay error vectors was examined over a large range of distances. The applications of CD-SEM overlay metrology were explored, and methodologies were introduced to examine both the overlay of double patterning contacts at the edge of an array and lithographic process-induced overlay shift of contacts. Finally, a hybrid optical CD-SEM overlay metrology was introduced in order to capture a high order, device weighted overlay response.

Integration of mask and silicon metrology in DFM

We have developed a highly integrated method of mask and silicon metrology. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. We have inspected the high accuracy, stability and reproducibility in the experiments of integration. The accuracy is comparable with that of the mask and silicon CD-SEM metrology. In this report, we introduce the experimental results and the application. As shrinkage of design rule for semiconductor device advances, OPC (Optical Proximity Correction) goes aggressively dense in RET (Resolution Enhancement Technology). However, from the view point of DFM (Design for Manufacturability), the cost of data process for advanced MDP (Mask Data Preparation) and mask producing is a problem. Such trade-off between RET and mask producing is a big issue in semiconductor market especially in mask business. Seeing silicon device production process, information sharing is not completely organized between design section and production section. Design data created with OPC and MDP should be linked to process control on production. But design data and process control data are optimized independently. Thus, we provided a solution of DFM: advanced integration of mask metrology and silicon metrology. The system we propose here is composed of followings. 1) Design based recipe creation: Specify patterns on the design data for metrology. This step is fully automated since they are interfaced with hot spot coordinate information detected by various verification methods. 2) Design based image acquisition: Acquire the images of mask and silicon automatically by a recipe based on the pattern design of CD-SEM.It is a robust automated step because a wide range of design data is used for the image acquisition. 3) Contour profiling and GDS data generation: An image profiling process is applied to the acquired image based on the profiling method of the field proven CD metrology algorithm. The detected edges are then converted to GDSII format, which is a standard format for a design data, and utilized for various DFM systems such as simulation. Namely, by integrating pattern shapes of mask and silicon formed during a manufacturing process into GDSII format, it makes it possible to bridge highly accurate pattern profile information over to the design field of various EDA systems. These are fully integrated into design data and automated. Bi-directional cross probing between mask data and process control data is allowed by linking them. This method is a solution for total optimization that covers Design, MDP, mask production and silicon device producing. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

Spatial signature in local overlay measurements: what CD-SEM can tell us and optical measurements can not

This work explores the applications of CD-SEM overlay metrology for double patterned one-dimensional (1D) pitch split features as well as double patterned ensembles of two-dimensional (2D) complex shapes. Overlay model analysis of both optical overlay and CD-SEM is compared and found to give nearly equivalent results. Spatial correlation of the overlay vectors is examined over a large range of spatial distances. The smallest spatial distances are shown to have the highest degree of correlation. Correlation studies of local overlay in a globally uniform environment, suggest that the smallest sampling of overlay vectors need to be ~10-15μm, within the spatial sampling of this experiment. The smallest spatial distances are also found to have to tightest mean distributions. The distribution width of the CD-SEM overlay is found to scale linearly with log of the spatial distances over 4-5 orders of magnitude of spatial length. Methodologies are introduced to examine both the overlay of double pattern contacts at the edge of an array and lithographic process-induced overlay shift of contacts. Finally, a hybrid optical- CD-SEM overlay metrology is introduced in order to capture a high order, device weighted overlay response.

New method of 2-dimensional metrology using mask contouring

We have developed a new method of accurately profiling and measuring of a mask shape by utilizing a Mask CD-SEM. The method is intended to realize high accuracy, stability and reproducibility of the Mask CD-SEM adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD measurement. In comparison with a conventional image processing method for contour profiling, this edge detection method is possible to create the profiles with much higher accuracy which is comparable with CD-SEM for semiconductor device CD measurement. This method realizes two-dimensional metrology for refined pattern that had been difficult to measure conventionally by utilizing high precision contour profile. In this report, we will introduce the algorithm in general, the experimental results and the application in practice. As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC (Optical Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the view point of DFM (Design for Manufacturability), a dramatic increase of data processing cost for advanced MDP (Mask Data Preparation) for instance and surge of mask making cost have become a big concern to the device manufacturers. This is to say, demands for quality is becoming strenuous because of enormous quantity of data growth with increasing of refined pattern on photo mask manufacture. In the result, massive amount of simulated error occurs on mask inspection that causes lengthening of mask production and inspection period, cost increasing, and long delivery time. In a sense, it is a trade-off between the high accuracy RET and the mask production cost, while it gives a significant impact on the semiconductor market centered around the mask business. To cope with the problem, we propose the best method of a DFM solution using two-dimensional metrology for refined pattern.