Yen-Kai Lin

Compact models of negative-capacitance FinFETs: Lumped and distributed charge models

This work presents insights into the device physics and behaviors of ferroelectric based negative capacitance FinFETs (NC-FinFETs) by proposing lumped and distributed compact models for its simulation. NC-FinFET may have a floating metal between ferroelectric (FE) and the dielectric layers and the lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used and at each point in the channel the ferroelectric layer will impact the local channel charge. This distributed effect has important implications on device characteristics as shown in this paper. The proposed compact models have been implemented in circuit simulators for exploring circuits based on NC-FinFET technology.

Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved

Negative capacitance field effect transistor (NCFET) is designed in 5-nm FinFET node, which simultaneously meets the low-power and high-performance targets of <inline-formula> <tex-math notation=LaTeX>

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Sensitivity in Presence of Parasitic Capacitance

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Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs

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Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

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Compact Modeling Source-to-Drain Tunneling in Sub-10-nm GAA FinFET With Industry Standard Model

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Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

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A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect

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Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor

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