Yen-Lung Chen

LASER: layout-aware analog synthesis environment on laker

In modern technology, layout effects have more and more impacts on circuit performance. However, most of the existing analog automation tools consider the circuit sizing and layout generation in two separate steps, which often result in time-consuming sizing-layout iterations. In this paper, a layout-aware analog synthesis tool is presented to generate the required designs from specifications to layout through a user-friendly GUI. In order to provide a strong link between sizing and layout steps, a parasitic-aware circuit sizing flow is proposed based on a flexible layout template to prevent the performance from failing to meet the specifications after layout. Routability-aware analog placement is then performed with a simple routing algorithm to generate the corresponding layout with minimized cost. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance with less over-design.

A bias-driven approach to improve the efficiency of automatic design optimization for CMOS OP-Amps

The equation-based analog design automation is getting popular in last decade to search the optimal solutions with good efficiency. However, due to the deep-submicron effects, significant modeling errors often exist in major transistor parameters like gds and gm. This often results in wrong prediction of circuit performance and leads to several redesign cycles to meet the specifications. Instead of building complex parameter models for gds and gm, this paper adopts the gm/Id design concept, which is an independent value to the device size, on equation-based optimization to solve the accuracy issue. Without the complex effects from W and L, the modeling accuracy of transistor parameters is significantly improved. No more iteration is required by using the proposed approach, which improves the efficiency as well as the accuracy. To the best of our knowledge, this is the first work that adopts the internal voltages instead of device sizes as the unknown variables to be solved. As demonstrated on several circuits with different objectives, both the accuracy and efficiency of circuit optimization can be improved significantly.

REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage

Statistical circuit simulation is exhibiting increasing importance for circuit design under process variations. Existing approaches cannot efficiently analyze the failure probability for circuits with a large number of variation, nor handle problems with multiple disjoint failure regions. The proposed rare event microscope (REscope) first reduces the problem dimension by pruning the parameters with little contribution to circuit failure. Furthermore, we applied a nonlinear classifier which is capable of identifying multiple disjoint failure regions. In REscope, only likely-to-fail samples are simulated then matched to a generalized pareto distribution. On a 108-dimension charge pump circuit in PLL design, REscope outperforms the importance sampling and achieves more than 2 orders of magnitude speedup compared to Monte Carlo. Moreover, it accurately estimates failure rate, while the importance sampling totally fails because failure regions are not correctly captured.

Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits

In advanced technology node, not only process variations but also aging effects have critical impacts on circuit performance. Most of existing works consider process variations and aging effects separately while building the corresponding behavior models. Because of the time-varied circuit property, parametric yield need to be reanalyzed in each aging time step. This results in expensive simulation cost for reliability analysis due to the huge number of circuit simulation runs. In this paper, an incremental Latin hypercube sampling (LHS) approach is proposed to build the stochastic behavior models for analog/mixed-signal (AMS) circuits while simultaneously considering process variations and aging effects. By reusing previous sampling information, only a few new samples are incrementally updated to build an accurate stochastic model in different time steps, which significantly reduces the number of simulations for aging analysis. Experiments on an operational amplifier and a DAC circuit achieve 242x speedup over traditional reliability analysis method with similar accuracies.

A layout-aware automatic sizing approach for retargeting analog integrated circuits

Automatically retargeting analog designs to new technology is an efficient solution for reusing analog IPs. However, most of previous approaches focus on layout retargeting only. How to obtain the new device sizes for another technology is often not discussed. Simply scaling the device sizes may not reach the desired performance due to the non-ideal effects. Therefore, a layout-aware automatic sizing flow for retargeting analog circuits is proposed in this paper. Based on the layout template extracted from the original design, the layout-induced parasitic effects in new technology are also considered in the sizing flow. Since the possible performance degradation has been considered, no redesign cycles and reserved design margins are required in the proposed sizing flow, which significantly reduces the design overhead. As shown in the experimental results, the design retargeting can be finished in one second by using the proposed flow, which demonstrates the feasibility and efficiency of this approach.

Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects

Flexible electronics are possible alternative for portable consumer applications with many advantages. However, the circuit design for flexible electronics is still challenging, especially for sensitive analog circuits. Significant parameter variations and bending effects of flexible TFTs further increase the difficulties for circuit designers. In this paper, an automatic circuit sizing technique is proposed for the analog circuits with flexible TFTs. The process variation and bending effects of flexible TFTs are considered simultaneously in the optimization flow. As shown in the experimental results, the proposed approach can further improve the design yield and significantly reduce the design overhead.

Layout-aware analog synthesis environment with yield consideration

With shrinking device size in deep submicron process, many non-ideal effects impact circuit performances critically. Since those effects are often not considered in traditional analog synthesis tools, several sizing-layout iterations are still required to reach the desired performance and design yield. In this paper, an integrated analog synthesis tool is presented to consider the process variation, layout effects, and final layout generation simultaneously, with a user-friendly GUI to help users complete the design flow efficiently. With the consideration of those non-ideal effects in early design stages, blind design margins and time-consuming re-design cycles can be avoided in the proposed tool, which significantly reduces the design overhead. As shown in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds and effectively guarantees the post-layout performance and design yield with less hardware cost.

Reliability-aware design automation flow for analog circuits

Manually designing analog circuits is often considered as a difficult task that takes a lot of time. If a design automation environment is available for analog circuits, it is useful for designers to cope with the increasing challenges in advance process. In this paper, a reliability-aware circuit sizing technique is proposed to consider process variation, circuit aging, and layout-dependent effects simultaneously. A reliability-aware analog layout automation technique is also proposed to consider both placement and routing while improving the reliability of the generated layout. These reliability-aware design automation techniques have been integrated to build a complete synthesis environment from specifications to layout. As shown in the experimental results, the proposed automation flow does help designers solve the reliability issues efficiently.

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only)

Software simulation of analog and mixed-signal circuits often takes a long computing time. Unlike digital circuits that can be validated by FPGA emulation, there is no winning emulation solution for analog circuits. As the first step to applying wave digital filter (WDF) to emulate post-layout analog circuits, we present how to map linear and nonlinear components in an original circuit to WDFs with exactly same behaviors. To validate, we implement the emulation circuit (i.e., WDFs) in FPGA. To be more specific, each emulation time step is executed as a finite state machine, while all the computing resource, e.g. floating point units (FPU), are shared as a resource pool and used only when it is necessary, which result in a very small resource consumption on FPGA. Virtually perfect match is obtained between the Verilog and SPICE simulations for a number of primitive analog circuits, indicating the high accuracy of the proposed emulation. In terms of runtime, the WDF implementation is about 3-4x faster than HSPICE on a small two-stage differential amplifier circuit. And better speedup can be anticipated when it scales to larger circuits because of the underlying binary tree structure of the WDF implementation.

Simultaneous optimization for low dropout regulator and its error amplifier with process variation

Due to its low power, small ripple and low noise properties, low-dropout regulators (LDO) are often used in on-chip applications. However, there are few design automation works focusing on this important circuit. In this paper, an automatic optimization process is proposed to generate the optimal sizing of low dropout regulators. The devices in the LDO circuit and its error amplifier are both considered in the optimization process for reducing the overall circuit cost. The process variation effects are also considered in this work to guarantee the circuit performance after manufactured. As demonstrated in the experiments, the proposed approach successfully solves the unreachable specification in previous work and significantly improves the design yield of the generated circuits.