Chien-Nan Jimmy Liu

A Tree-Topology Multiplexer for Multiphase Clock System

This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show that the proposed design can achieve higher bandwidth and be less sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- mum CMOS technology. Measured results indicate that the proposed design can operate up to 7 gigabits/s under 0.3-UI jitter limitation.

Hybrid Approach to Faster Functional Verification with Full Visibility

For functional verification, software simulation provides full controllability and observability, whereas hardware emulation offers speed. This article describes a new platform that leverages the advantages of both. This platform implements an efficient scheme to record the internal behavior of an FPGA emulator and replay the relevant segment of a simulation in a software environment for debugging. Experimental results show an order-of-magnitude savings in debugging time compared to a software-only simulation approach.

Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models

Using the behavioral model of a circuit to perform behavioral Monte Carlo simulation (BMCS) is a fast approach to estimate performance shift under process variation with detailed circuit responses. However, accurate Monte Carlo analysis results are difficult to obtain if the behavioral model is not accurate enough. Therefore, this paper proposes to use an efficient bottom-up approach to generate accurate process-variation-aware behavioral models of CPPLL circuits. Without blind regressions, only one input pattern in the extraction mode sufficiently obtains all required parameters in the behavioral model. A quasi-SA approach is also proposed to accurately reflect process variation effects. Considering generic circuit behaviors, the quasi-SA approach saves considerable simulation time for complicated curve fitting but still keeps estimation accuracy. The experimental results demonstrate that the proposed bottom-up modeling flow and quasi-SA equations provide similar accuracy as in the RSM approach, using less extraction cost as in the traditional sensitivity analysis approach.

An automatic controller extractor for HDL descriptions at the RTL

Extracting controlling finite-state machines can significantly reduce state space and thereby speed functional verification. The controller extraction algorithm uses an approach that frees it from restrictions on HDL code writing style.

Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging

When hardware description languages (HDLs) are used in describing the behavior of a digital circuit, design errors (or bugs) almost inevitably appear in the HDL code of the circuit. Existing approaches attempt to reduce efforts involved in this debugging process by extracting a reduced set of error candidates. However, the derived set can still contain many error candidates, and finding true design errors among the candidates in the set may still consume much valuable time. A debugging priority method was proposed to speed up the error-searching process in the derived error candidate set. The idea is to display error candidates in an order that corresponds to an individuals degree of suspicion. With this method, error candidates are placed in a rank order based on their probability of being an error. The more likely an error candidate is a design error (or a bug), the higher the rank order that it has. With the displayed rank order, circuit designers should find design errors quicker than with blind searching when searching for design errors among all the derived candidates. However, the currently used confidence score (CS) for deriving the debugging priority has some flaws in estimating the likelihood of correctness of error candidates due to the masking error situation. This reduces the degree of accuracy in establishing a debugging priority . Therefore, the objective of this work is to develop a new probabilistic confidence score (PCS) that takes the masking error situation into consideration in order to provide a more reliable and accurate debugging priority. The experimental results show that our proposed PCS achieves better results in estimating the likelihood of correctness and can indeed suggest a debugging priority with better accuracy, as compared to the CS.

A novel approach for functional coverage measurement in HDL

While the coverage-driven functional verification is getting popular, a fast and convenient coverage measurement tool is necessary. In this paper, we propose a novel approach for functional coverage measurement based on the VCD files produced by the simulators. The usage flow of the proposed dumpfile-based coverage analysis is much easier and smoother than that of existing instrumentation-based coverage tools. No pre-processing tool is required and no extra code will be inserted into the source code. Most importantly, the flexibility in choosing coverage metrics and measured code regions is increased. Only one simulation run is needed for any kind of coverage reports. By conducting some experiments on real examples, it shows very promising results in terms of the performance and the accuracy of coverage reports.

LASER: layout-aware analog synthesis environment on laker

In modern technology, layout effects have more and more impacts on circuit performance. However, most of the existing analog automation tools consider the circuit sizing and layout generation in two separate steps, which often result in time-consuming sizing-layout iterations. In this paper, a layout-aware analog synthesis tool is presented to generate the required designs from specifications to layout through a user-friendly GUI. In order to provide a strong link between sizing and layout steps, a parasitic-aware circuit sizing flow is proposed based on a flexible layout template to prevent the performance from failing to meet the specifications after layout. Routability-aware analog placement is then performed with a simple routing algorithm to generate the corresponding layout with minimized cost. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance with less over-design.

A bias-driven approach to improve the efficiency of automatic design optimization for CMOS OP-Amps

The equation-based analog design automation is getting popular in last decade to search the optimal solutions with good efficiency. However, due to the deep-submicron effects, significant modeling errors often exist in major transistor parameters like gds and gm. This often results in wrong prediction of circuit performance and leads to several redesign cycles to meet the specifications. Instead of building complex parameter models for gds and gm, this paper adopts the gm/Id design concept, which is an independent value to the device size, on equation-based optimization to solve the accuracy issue. Without the complex effects from W and L, the modeling accuracy of transistor parameters is significantly improved. No more iteration is required by using the proposed approach, which improves the efficiency as well as the accuracy. To the best of our knowledge, this is the first work that adopts the internal voltages instead of device sizes as the unknown variables to be solved. As demonstrated on several circuits with different objectives, both the accuracy and efficiency of circuit optimization can be improved significantly.

Design of an All-Digital LVDS Driver

This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-mum 1P6M CMOS process with a core area of 0.072 mm2. At 3 Gbps, it consumes 9 mW of power under a 1.8-V power supply or 3 pJ/bit.

A Scalable Digitalized Buffer for Gigabit I/O

A serial input-output (I/O) composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the simultaneous switching noise simultaneously. With a TSMC 0.18-mum CMOS process, the I/O occupies an area of 0.014 mm2 and operates from 4 Gbps@1.9 V to 1.5 Gbps@1.1 V.