Chin-Cheng Kuo

Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models

Using the behavioral model of a circuit to perform behavioral Monte Carlo simulation (BMCS) is a fast approach to estimate performance shift under process variation with detailed circuit responses. However, accurate Monte Carlo analysis results are difficult to obtain if the behavioral model is not accurate enough. Therefore, this paper proposes to use an efficient bottom-up approach to generate accurate process-variation-aware behavioral models of CPPLL circuits. Without blind regressions, only one input pattern in the extraction mode sufficiently obtains all required parameters in the behavioral model. A quasi-SA approach is also proposed to accurately reflect process variation effects. Considering generic circuit behaviors, the quasi-SA approach saves considerable simulation time for complicated curve fitting but still keeps estimation accuracy. The experimental results demonstrate that the proposed bottom-up modeling flow and quasi-SA equations provide similar accuracy as in the RSM approach, using less extraction cost as in the traditional sensitivity analysis approach.

Fast and Accurate Analysis of Supply Noise Effects in PLL With Noise Interactions

Using behavioral models to perform fast simulation is currently a popular solution to verify SOC designs. Previous analog behavior modeling approaches often treat the noisy VDD waveform as a given input and focus on reflecting such stimuli on circuit performance. However, because the interaction of noise aggressors and victims is not considered, some error may exist while compared with real simulation results. In this paper, a simple SCORE macromodel is proposed for PLL designs to help noise-aware behavioral models handle supply noise interaction effects. The time-varying supply noise waveform and real-time PLL responses can be obtained simultaneously with accurate noise estimations in this recursive approach. As demonstrated in the experimental results, the proposed approach can provide more realistic results with noise interaction effects but still keep fast simulation time.

On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems

Using behavioral models to perform system simulation at behavioral level is currently a popular solution to verify SOC designs. For analog behavioral models, most of previous approaches are developed with the assumption that noise waveforms are known functions, such as sinusoid waves or Gaussian noise. However, while co-simulated with other blocks in the system, the actual supply noise induced by other circuits is often very irregular and unpredictable. Therefore, the simulation results may still have some errors in real environment. In this paper, an efficient behavioral modeling approach for PLL designs is proposed to analyze the real-time supply noise effects. Instead of directly modeling the final circuit performance as a single complicated equation, we try to model suitable intermediate parameters whose relationship to supply noise is much simpler. The experimental results have shown that our approach can accurately deal with irregular noise with such a simple model

Accurate behavioral modeling approach for PLL designs with supply noise effects

Using behavioral models to perform system simulation at behavioral level is currently a popular solution to verify mixed-signal systems. However, most of existing approaches only deal with ideal environments or make unrealistic assumptions, which cannot accurately evaluate the performance under supply voltage variation. In this paper, an efficient modeling approach with the effects of supply voltage variation is presented for PLL circuits to build accurate behavioral models in a short time using bottom-up extraction. Only three post-layout simulations are enough to generate accurate behavioral models under different supply voltages. The experimental results have shown that this approach can really have accurate responses under different supply voltages without time-consuming correlation analysis.

An accurate PLL behavioral model for fast Monte Carlo analysis under process variation

Hierarchical statistical analysis using the regression-based approach is often used to improve the extremely expensive HSPICE Monte Carlo (MC) analysis. However, accurately fitting the regression equations requires many simulation samples. In this paper, an accurate behavioral Monte Carlo simulation (BMCS) approach to analyze PLL designs under process variation is developed by building a bottom-up behavioral modeling approach with an efficient extraction process. Using the accurate model, we also develop a modified sensitivity analysis for process variation effects to provide accurate enough results with less regression cost. As shown in the experimental results, we reduce the simulation time of HSPICE MC analysis from several weeks to several hours and still retain similar statistical results as in HSPICE MC simulation.

A fast heuristic approach for parametric yield enhancement of analog designs

In traditional yield enhancement approaches, a lot of computation efforts have to be paid first to find the feasible regions and the Pareto fronts, which will become a heavy cost for large analog circuits. In order to reduce the computation efforts, this article proposes a fast heuristic approach that tries to finish all iteration steps of the yield enhancement flow at behavior level. First, a novel force-directed Nominal Point Moving (NPM) algorithm is proposed to find a better nominal point without building the feasible regions. Then, an equation-based behavior-level sizing approach is proposed to map the NPM results at performance level to behavior-level parameters. A fast behavior-level Monte Carlo simulation is also proposed to shorten the iterative yield enhancement flow. Finally, using the obtained behavioral parameters as the sizing targets of each subblock, the device sizing time is significantly reduced instead of sizing from the system-level specifications directly. As demonstrated on several analog circuits, this heuristic approach could be another efficient methodology to help designers improve their analog circuits toward better yield.

An efficient bottom-up extraction approach to build the behavioral model of switched-capacitor ΔΣ modulator

In this paper, an efficient bottom-up extraction approach is proposed to build accurate behavioral model for the switched-capacitor (SC) delta-sigma (DeltaSigma) modulator. In the special extraction mode, we can use several specific patterns to obtain the key circuit parameters of the design in a short time without separating it into several sub-blocks. Actual loading effects and parasites can be considered automatically, which makes our modeling approach become more suitable for existed IPs and flattened post-layout designs. In the experiments, the comparison results between our behavioral model and HSPICE simulation have demonstrated the accuracy and efficiency of the proposed modeling strategy.

Behavior-level yield enhancement approach for large-scaled analog circuits

In traditional yield enhancement approaches, a lot of computation efforts have to be paid first to find the feasible regions and the Pareto fronts, which will become a heavy cost for large analog circuits. In order to reduce the computation efforts, this work tries to finish all iteration steps of the yield enhancement flow at behavior level. First, a novel force-directed nominal point moving (NPM) algorithm is proposed to find a better nominal point without building the feasible regions. Then, an equation-based behavior-level sizing approach is proposed to map the NPM results at performance level to behavior-level parameters. A fast behavior-level Monte Carlo simulation is also proposed to shorten the iterative yield enhancement flow. Finally, using the obtained behavioral parameters as the sizing targets of each sub-block, the device sizing time is significantly reduced instead of sizing from the system-level specifications directly. As demonstrated on a complex CPPLL design, this behavior-level approach could be another efficient methodology to help designers improve their analog circuits toward better yield.

A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level

Using behavioral models to perform fast simulation is currently a popular solution to verify SOC designs. Previous analog behavior modeling approaches often treat the noisy VDD waveform as a given input and focus on reflecting such stimuli on circuit performance. However, because the interaction of noise aggressors and victims is not considered, some errors may exist in the simulation. In this paper, a simple SCORE macromodel is proposed for PLL designs. It can be integrated with a supply-noise-aware PLL behavioral model to analyze supply noise effects at high level. In addition to numerical results, the time-varying supply noise waveform and real-time PLL responses can be obtained simultaneously. As demonstrated in the experimental results, the proposed approach can provide more realistic simulation results with noise interaction effects but still keep fast simulation time.