Yen T. Chen

Intrinsic SiOx-based unipolar resistive switching memory. I. Oxide stoichiometry effects on reversible switching and program window optimization

The physical mechanisms of unipolar resistive switching (RS) in SiOx-based resistive memory are investigated using TaN/SiOx/n++Si and TiW/SiOx/TiW device structures. RS is independent of SiOx thickness and device area, confirming that RS occurs in a localized region along a filamentary pathway. Results from experiments varying electrode type, series resistance, and the oxygen content of SiOxNy materials show the potential to optimize switching performance and control device programming window. Device materials with stoichiometry near that of SiO2 are found to have better operating stability as compared to extrinsic, N-doped SiOxNy materials. The results provide further insight into the physical mechanisms of unipolar operation and lead to a localized switching model based on electrochemical transitions involving common SiOx defects. High-temperature data retention measurements for over 104 s in high- and low-resistance states demonstrate the potential for use of intrinsic SiOx RS devices in future nonvola...

Metal-oxide-semiconductor field-effect-transistors on indium phosphide using HfO2 and silicon passivation layer with equivalent oxide thickness of 18 Å

In this letter, we demonstrate the electrical properties of metal-oxide-semiconductor capacitors and metal-oxide-semiconductor field-effect transistors (MOSFETs) on InP using atomic layer deposited HfO2 gate dielectric and a thin silicon interface passivation layer (Si IPL). Compared with single HfO2, the use of Si IPL results in better interface quality with InP substrate, as illustrated by smaller frequency dispersion and reduced hysteresis. MOSFETs with Si IPL show much higher drive current and transconductance, improved subthreshold swing, interface-trap density and gate leakage current with equivalent oxide thickness scaling down to 18 A.

Electroforming and resistive switching in silicon dioxide resistive memory devices

Electroforming and resistive switching in SiO2 materials are investigated by controlling the annealing temperature, etching time and operating ambient. Thermal anneal in reducing ambient lowers electroforming voltage to 10 nm from the electrode edge in devices with continuous SiO2 layers. Switching unpassivated devices fails in 1 atm air and pure O2/N2, with the recovery of vacuum switching at ∼4.6 V after switching attempts in O2/N2 and at ∼9.5 V after switching attempts in air. Incorporating a hermetic passivation layer enables switching in 1 atm air. Discussions of defect energetics and electrochemical reactions lead to a localized switching model describing device switching dynamics. Low-frequency noise data are consistent with charge transport through electron-trapping defects. Low-resistance-state current for <1.5 V bias is modeled by hopping conduction. A current “overshoot” phenomenon with threshold near 1.6 V is modeled as electron tunneling. Results demonstrate that SiO2-based resistive memory devices provide a good experimental platform to study SiO2 defects. The described electroforming methods and operating models may aid development of future SiO2-based resistive memory products.

Discussion on device structures and hermetic encapsulation for SiOx random access memory operation in air

An edge-free structure and hermetic encapsulation technique are presented that enable SiOx-based resistive random-access memory (RRAM) operation in air. A controlled etch study indicates that the switching filament is close to the SiOx surface in devices with an exposed SiOx edge. Electrical test of encapsulated, edge-free devices in 1 atmosphere air indicates stable switching characteristics, unlike devices with an edge. This work demonstrates that SiOx RRAM is able to operate in air with proper encapsulation and an edge-free structure. The resistive switching failure mechanism when operating in air is explained by the oxidation of hydrogen-complexed defects in the switching filament.

Acute high-intensity exercise-induced cognitive enhancement and brain-derived neurotrophic factor in young, healthy adults.

Acute exercise can positively impact cognition. The present study examined the effect of acute high-intensity aerobic exercise on prefrontal-dependent cognitive performance and brain-derived neurotrophic factor (BDNF). Fifty-eight young adults were randomly assigned to one of two experimental groups: (a) an acute bout of high-intensity exercise (n=29) or (b) a non-exercise control (n=29). Participants in the exercise group improved performance on inhibitory control in Stroop interference and on cognitive flexibility in Trail Making Test (TMT) Part-B compared with participants in the control group and increased BDNF immediately after exercise. There was a significant relationship between BDNF and TMT Part-B on the pre-post change following exercise. These findings provide support for the association between improved prefrontal-dependent cognitive performance and increased BDNF in response to acute exercise. We conclude that the changes in BDNF concentration may be partially responsible for prefrontal-dependent cognitive functioning following an acute bout of exercise.

Effects of InP barrier layer thicknesses and different ALD oxides on device performance of In 0.7 Ga 0.3 As MOSFETs

III–V materials are attractive for achieving enhanced device performance due to their high electron mobility. It has been reported that buried channel InGaAs MOSFETs with barrier layers¹⁻³ can achieve much higher electron mobility than surface channel InGaAs MOSFETs⁴⁻⁵ and several orders lower gate leakage current than HEMTs⁶. However, the effects of barrier layer thicknesses and oxide/barrier interface quality on device performance have not been studied. In this paper, InP barrier was used instead of InAlAs barrier due to its better interface quality with gate oxides⁷. The effects of different InP barrier thicknesses on device performance were investigated. We have also deposited different ALD gate oxides (single Al<inf>2</inf>O<inf>3</inf>, HfO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf>/HfO<inf>2</inf> bilayer) and studied the influence of various oxides on oxide/barrier interface and device characteristics. Equivalent oxide thicknesses (EOT) of In<inf>0.7</inf>Ga<inf>0.3</inf>As MOSFETs with InP barrier have been scaled to 1.2 nm using HfO<inf>2</inf>. Record high effective channel mobility μ<inf>eff</inf> of 4584 cm²/Vs and small subthreshold swing of 96 mV/dec have been achieved using 5 nm InP barrier and 4 nm Al<inf>2</inf>O<inf>3</inf> oxide. Ring-type In<inf>0.7</inf>Ga<inf>0.3</inf>As MOSFETs were fabricated on MBE 10nm undoped In<inf>0.7</inf>Ga<inf>0.3</inf>As channel with two different InP barrier thicknesses (3 nm & 5 nm) (fig.1). The n⁺ InGaAs contact layer was selectively removed at channel region. Various gate oxides (4 – 8 nm Al<inf>2</inf>O<inf>3</inf>, 5 nm HfO<inf>2</inf> and 1 nm Al<inf>2</inf>O<inf>3</inf>/4 nm HfO<inf>2</inf> bilayer) were deposited by ALD. After that, TaN was deposited for gate electrode and AuGe/Ni/Au for source and drain ohmic contact.

Nonplanar InGaAs Gate Wrapped Around Field-Effect Transistors

Nonplanar In_0.53Ga_0.47As gate wrap around field-effect transistors (GWAFETs) with atomic-layer deposited high-k dielectric and metal gate have been demonstrated in this paper. By applying novel device structure and optimizing fabrication process, In_0.53Ga_0.47As GWAFETs exhibit significant performance improvements over planar MOSFETs on both current drive capability and electrostatics control. In_0.53Ga_0.47As GWAFETs with fin width (W_fin) 40-200 nm have been fabricated. Devices with narrower W_fin exhibit higher drive current, transconductance, and better short channel effect control, which demonstrates the scalability of nonplanar In_0.53Ga_0.47As GWAFETs. Subthreshold swing of 80 mV/decade and drain-induced barrier lowering of 20 mV/V have been achieved by 40-nm W_fin and 140-nm L_g In_0.53Ga_0.47As GWAFETs.

Study of ambient effect in active SiO x -based resistive switching memory

The active element of unipolar SiOx-based resistive switching (RS) memory has been investigated. Testing over a range of temperatures and in different ambients provide information regarding filament growth characteristics and a possible packaging solution. Plausible SiOx-based RS mechanisms are modeled and proposed based on trap transformation between H-bridge and H-doublet oxygen vacancy defects. Excellent reliability in multilevel operation and pulse response in the 50 ns regime demonstrates good potential for high-density, high-speed SiOx-based RS memory.

Physical Fitness, Grit, School Attendance, and Academic Performance among Adolescents

Objective The purpose of this study was to examine the relationship of grit as a construct representing perseverance to overcoming barriers and the total number of school absences to academic performance (AP) while controlling for sociodemographics, fitness (i.e., PACER), and Body Mass Index (BMI). Methods Adolescents (N = 397, SD = 1.85; 80.9% females; 77.1% Hispanic) from an urban, minority-majority city in the Southern United States completed the FitnessGram® assessment of physical fitness (e.g., aerobic capacity and Body Mass Index (BMI)) and the valid and reliable short grit survey. The schools provided sociodemographics, attendance, and AP data for the adolescents. Results Adolescents with higher grit scores (rs = 0.21, P < 0.001) and less total absences (rs = −0.35, P < 0.001) performed better on AP. Hierarchical multiple regression indicated that grit and absences were associated with AP (β = 0.13, P < 0.01 and β = −0.35, P < 0.001, resp.). Conclusions Grit and a total number of absences are significant contributors to academic success, particularly among Hispanic adolescents. Further, grit and school attendance may serve as a better measure of protective factors over proximal health measures of cardiovascular health and BMI.

Leisure-Time Physical Activity, Subjective Age, and Self-Rated Memory in Middle-Aged and Older Adults:

Memory concerns are common in middle-aged and older adults. This study investigated the relation of leisure-time physical activity to self-rated memory and the possible mediating role of subjective age in this relationship in middle-aged and older adults. Cross-sectional analyses were conducted with a sample of 1,608 middle-aged and older adults from the second wave of the National Survey of Midlife Development in the United States (MIDUS2). In a path analysis conducted with Mplus, a higher level of leisure-time physical activity was associated with a more positive appraisal of memory compared to others of one’s age; younger subjective age partially mediated this relationship. Neither gender nor age-group moderated the association. Age, race, education, marital status, health status, and negative affect were controlled for in the analyses. These findings suggest a possible role of physical activity in countering the effects of age stereotypes on perceived memory.