Yeur-Luen Tu

A leading-edge 0.9µm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling

This paper presents process breakthroughs that enable a BSI 0.9µm pixel formation and its performance. The technology was developed using 300mm bulk silicon starting wafers with the state-of-the-art tool set for BSI sensor processing. This is the first demonstration of 0.9µm BSI pixel with acceptable optical performance. Further improvements are in the area of crosstalk suppression and color performance enhancement for continuous pixel scaling from 0.9µm.

High performance 300mm backside illumination technology for continuous pixel shrinkage

Backside Illumination (BSI) sensor with excellent optical performance has become the main-stream CMOS image sensor process. This work addressed the key factors and issues for 300mm BSI technology, including wafer distortion, silicon thickness variation, backside junction formation and dielectric film structure, thermal annealing and so on. It is demonstrated that with the optimized key process, a high performance 0.9um BSI pixel with low noise can be fabricated.

Using an ammonia treatment to improve the floating-gate spacing in split-gate flash memory

In the split-gate flash memory process, during poly oxidation, the birds beak encroaches under the SiN film, especially along the poly grain boundary, and that will cause nonuniform floating-gate (FG) spacing, even bridging, which is an obstacle to cell shrinkage. In this paper, we show that employing an ammonia treatment on the poly can nitridize the poly surface, thereby avoiding birds beak bridging. After the ammonia treatment, FG spacing is quite uniform and can be improved from 0.09 to 0.03 /spl mu/m. The XPS analysis on the ammonia treated poly shows the oxynitride thickness is less than 5 nm.

Plasma charging defect characterization, inspection, and monitors in poly-buffered STI

In this paper, the mechanism, inspection, and inline monitor of plasma charging defects found in an active area (AA) corner and edge using a poly-buffer (PB) STI process is reported. These defects are formed by the arcing (or discharging) through weak spots of pad-oxide between the poly-buffer layer and substrate as resulting from the charging of poly buffer layer during reverse-AA oxide etching. Such defect formation is found to be strongly enhanced by the magnetic field used in oxide etchers but not related to etch rate and plasma density. The defect inspection on patterned wafers is found to be strongly correlated to the flat-band voltage (V/sub fb/) and to a lesser extent to oxide charge (Q/sub tot/) degradation on in-line unpatterned oxide wafers. Therefore, the shift of V/sub tb/ and Q/sub tot/ on unpatterned wafers can be effective inline monitors for plasma charging damage during reverse-AA etching in PB-STI process.

Advanced device performance impact by wafer level 3D stacked architecture

A high density 50K~100K/mm2 cross-tier connection featuring backside through-via (BTV) and wafer level 3D stacking technologies has been successfully demonstrated. Wafer stacking and thinning to <; 1/250 Si thickness process showed little to no impact to advanced device performance. BTV induced stress effect was also studied; quite different behaviors between wafers with SiGe and without SiGe process were found. SiGe local strain will be diminished by BTV induced strain when BTV getting too close to channel, and hence lower hole mobility. This impact could be minimized by proper Keep-Out Zone (KOZ) design. Furthermore, 3D stacked architecture provides the opportunity to individually optimize process and design for each function block on separated wafers, thus improve chip performance and power consumption, and also benefit chip footprint.